https://e2e.ti.com/support/rf-microwave-group/rf-microwave/Products covered in this section are Digital Radio (Gray Chip) Products. en-USTelligent Community 13https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1643692/afe8192-afe8192-design-document/6337350Fri, 08 May 2026 02:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:05f48ce5-93cb-423e-84b1-6eab737123e4Kang HsiaHi Eddie, Could you please request the information from the link below? Thanks! https://www.ti.com/drr/opn/AFE81XX-WI-DESIGN -Kanghttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1643692/afe8192-afe8192-design-documentFri, 08 May 2026 01:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2bd858f3-7fd0-49b3-88cf-9106400c99c4Eddie LiaoPart Number: AFE8192 Hi Sir Do you have full design document of AFE8192? Could you provide it to me, please? Best regards, EddieAFE8192https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1639464/amc7908evm-amc7908evm-sparked-and-blew-up/6337037Thu, 07 May 2026 20:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bf2c5e64-bf1b-4181-b4fd-7edb8395af7eErin BowrieHi Nathan, I don't see anything particularly wrong with your setup; Do note that by default, the ADC starts in Auto conversion mode, so you won't see the "ADC_BUSY" flag in the gen status register go low once you trigger the ADC. Are your output pins floating or tied to a PA when you're running this test? I'm still not seeing sparking when I use your setup, but my pin is floating. If you are using a PA, there may be some play between the PA gate and the device. Thanks, Erinhttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1643354/afe7900-ti-ip-supported-in-newer-versions-of-vivadoThu, 07 May 2026 08:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:402a3635-d5a0-4235-b91e-91d9e2c0f476SMPart Number: AFE7900 Hello, We are seeing the following error: TI_204c_IP_xilinx.svp cannot decrypt IEEE-1735 envelope: When upgrading a 2020.1 project to 2024.1 we are getting the following error: [#UNDEF] Cannot decrypt IEEE-1735 envelope: key value doesn't match key name "xilinxt_2017_05" (perhaps the public key was incorrect at encryption time). Thank you for your time,Wireless InfrastructureAFE7900https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1639464/amc7908evm-amc7908evm-sparked-and-blew-up/6335551Thu, 07 May 2026 00:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9b65c414-eebc-4f82-b3f6-7be803ee18e8Nathan KiddHere is the series of commands I give. These are taken out of context, so this is not representative of the program I have, but is representative of the order in which all the commands are issued. I'll note that this does work (when the power supply is on, of course). The idea is to do the following: 1. Initialize 2. Set gate voltage 3. Loop a,b,c 5 times 3.a. Turn on gate - *pause* 3.b. Take current measurement 3.c. Turn off gate - *pause* 4. Do calculations and pause 5. Repeat 2, 3, 4 as desired Somewhere in step 3 it sparked, it never reached step 4. Initialization : 1. chip_id = read_register_paged(_GLOBAL_PAGE, _CHIP_ID_REGISTER) 2. chip_ver = read_register_paged(_GLOBAL_PAGE, _CHIP_VER_REGISTER) 3. update_paged_register( _DAC_CONFIG_PAGE, _DAC_CFG_REGISTER, lambda v: _set_bit(v, _DACA_BIPOLAR_BIT, False) ) 4. update_paged_register( _GLOBAL_PAGE, _PWR_EN_REGISTER, lambda v: _set_bit(_set_bit(v, _PWR_EN_DACA0_BIT, True), _PWR_EN_DACA1_BIT, True) ) 5. update_paged_register( _GLOBAL_PAGE, _DRVEN_SW_EN_REGISTER, lambda v: _set_bit(_set_bit(v, _DRVEN_SW_EN_DACA0_BIT, True), _DRVEN_SW_EN_DACA1_BIT, True) ) 6. update_paged_register( _DAC_CONFIG_PAGE, _DAC_CFG_REGISTER, lambda v: _set_bit(v, _CLAMP_SEL_OUTA0_BIT, True) ) 7. write_register_paged(_DAC_BUFFER_PAGE, _DACA0_BUFFER_REGISTER, code) --- used code for 1.5V 8. write_register_paged(_DAC_BUFFER_PAGE, _DACA1_BUFFER_REGISTER, code) --- used code for 0V 9. self._update_paged_register( _GLOBAL_PAGE, _DRVEN_REGISTER, lambda v: _set_bit(_set_bit(v, _DRVEN_DACA0_BIT, enabled), _DRVEN_DACA1_BIT, True) ) 10. update_paged_register( _GLOBAL_PAGE, _DRVEN_SW_EN_REGISTER, lambda v: _set_bit(v, _DRVEN_SW_EN_DACA0_BIT, True) ) 11. update_paged_register( _DAC_CONFIG_PAGE, _DRVEN0_EN_REGISTER, lambda v: _set_bit(v, _DRVEN0_EN_DACA0_BIT, False) ) 12. update_paged_register( _DAC_CONFIG_PAGE, _DRVEN1_EN_REGISTER, lambda v: _set_bit(v, _DRVEN1_EN_DACA0_BIT, False) ) 13. update_paged_register( _DAC_CONFIG_PAGE, _FLEXIO_EN_REGISTER, lambda v: _set_bit(v, _FLEXIO_EN_DACA0_BIT, False) ) Test Loop: 14. write_register_paged(_DAC_BUFFER_PAGE, _DACA1_BUFFER_REGISTER, code) --- used code for 1.2V loop 5x { 15. update_paged_register( _GLOBAL_PAGE, _DRVEN_REGISTER, lambda v: _set_bit(_set_bit(v, _DRVEN_DACA0_BIT, True), _DRVEN_DACA1_BIT, True) ) -- pause -- 16. write_register_paged(_GLOBAL_PAGE, _TRIGGER_REGISTER, (1 0b00000000 4. Write: Page 0x00, Reg 0x08 --> 0b00000011 5. Write: Page 0x00, Reg 0x12 --> 0b00000011 6. Write: Page 0x03, Reg 0x42 --> 0b00000001 7. Write: Page 0x04, Reg 0x40 --> 0b0000010011001101 (0x04cd, 1229 counts, 1.5V) 8. Write: Page 0x04, Reg 0x41 --> 0b0000000000000000 (0x000, 0 counts, 0V) 9. Write: Page 0x00, Reg 0x13 --> 0b00000011 10. Write: Page 0x00, Reg 0x12 --> 0b00000001 11. Write: Page 0x03, Reg 0x50 --> 0b00000000 12. Write: Page 0x03, Reg 0x51 --> 0b00000000 13. Write: Page 0x03, Reg 0x52 --> 0b00000001 Test Loop 14. Write: Page 0x04, Reg 0x41 --> 0b0000001111010111 (0x03d7, 983 counts, 1.2V) loop 5x { 15. Write: Page 0x00, Reg 0x13 --> 0b00000011 -- pause -- 16. Write: Page 0x00, Reg 0x12 --> 0b00000001 17. Read: Page 0x00, Reg 0x03 --- keep reading this on a loop until conversion is complete for a max of 5ms 18. Read: Page 0x00, Reg 0x18 19. Write: Page 0x00, Reg 0x10 --> 0b00000010 -- pause -- } SPARK! --------- Thanks for all your help, Nathanhttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1639464/amc7908evm-amc7908evm-sparked-and-blew-up/6335510Wed, 06 May 2026 23:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5c24e854-6322-4a18-82ce-e467f096ab9fErin BowrieHi Nathan, Well, that's an unfortunate turn of events... The USB causing the board to go hot is an interesting clue. The USB is set up to power VIO and VDD by default, so if the board feels hot with it plugged in that means VDD is likely busted and drawing extra current. Remove the J13 VDD jumper and apply power externally to the J5 banana jack. If it draws a high amount of current, that may be part of our culprit. If it doesn't, try VIO as well (I wouldn't expect VIO to break like this though). It looks like your VSS is also drawing high current, 300mA is very high. It looks like the black marks on the die are close to the VCCB/A inputs. May be a trick of the light, but the VCCB pad looks different than the other pads. This may be more clues that VCC turning off is causing our issue here. Can you give me a detailed list of register writings you're using before the board blows up? I'd like to try to recreate the experiment. Thanks, Erinhttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1639464/amc7908evm-amc7908evm-sparked-and-blew-up/6335468Wed, 06 May 2026 22:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b65b64ce-6333-4466-95a2-bfa3ad5c1becNathan KiddErin, 1) Not sure how to test all of these, since I thought the jumpers automatically controlled the voltage output on these ports? On Vcca, 0A with 5V applied. On Vss, 0.3A with 0V applied (sinking into power supply somehow). The VIO and VDD had voltages on them. 2) There aren't, however the AMC has visible holes in the package. In addition, the AMC gets very hot when the USB cable is plugged in, even when nothing else is plugged in. It cools when the USB cable is disconnected 3) I had a communication loop going which was telling the AMC in software to turn on and off the gate voltage (I now realize it wasn't in DRVEN mode, it was being controlled by software). I believe it was working for a little while before crashing out. Finally, the replacement kit you sent also burnt out... I disconnected the FGEN which was pulsing the DRVEN completely as I feared it was causing an issue, then ran my test again. During my testing, the power supply once again got turned off (possibly my program is doing this??? not exactly your problem but why is it off!!! UGH) and just during software gate "on-off-ing" it broke the same way after 5 pulses, with little holes in the same place. Nathanhttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1629534/afe7900-nco-phase-accumulator-reset-after-freq-change/6335047Wed, 06 May 2026 16:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:abd9ed6d-b4f3-47c6-b84f-3f37f3aca0caDavid ChaparroHi Arye, Can you please share more information on what exactly you are trying to achieve by resetting the phase accumulator? With only a single device there should not be a need to reset the phase as all channels will be aligned and the AFE maintains the phase of each NCO when not in use. Regards, David Chaparrohttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1643093/lmx2695sepevm-is-there-a-datasheet-available-for-the-lmx2624-lmx2695-sep/6335036Wed, 06 May 2026 16:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4ff8a7d3-ffb8-4c1b-a162-b958b827bccaNoel FungHi There, SP (or SHP) and SEP devices have different radiation immunity level, the functionality and electrical performance are usually identical. LMX2595 is an industrial grade device.https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1630908/afe7900-unexpected-behaviour-of-rx-channel-in-system-mode-3/6334958Wed, 06 May 2026 15:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f5b2721-af22-4836-a93b-f2aab2cf0570David ChaparroHi Noumeer, I believe the reason you are seeing this is because of a combination of your bandwidth/interface rate and NCO settings. With an interface rate of 368.64Msps and NCO of 120MHz, you are capturing data from 120+/- 184.32MHz. This means that you are capturing the DC spur which may be causing the issue you are seeing. I recommend updating the NCO such that the DC spur is not in band and this should go away. Regards, David Chaparrohttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1643144/afe7950-afe7950-zcu102-contractorWed, 06 May 2026 15:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ee1d8312-1001-4975-b0d6-b035fc37de28JT MillerPart Number: AFE7950 We are interested in migrating a TI-supplied AFE7950EVM reference design to a custom ZCU102 design. This would involve replacing the Microblaze with the A53 and refining the 80k SPI register writes with only the necessary writes. Does TI have any list of contractors which could support this work?AFE7950EVMAFE7950Wireless Infrastructurehttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1630908/afe7900-unexpected-behaviour-of-rx-channel-in-system-mode-3/6334807Wed, 06 May 2026 14:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9805e14a-787f-4fff-ac31-c4e7a0f1707fNoumeer PirachaAre there any other possible reasons for observing this type of waveform? The ADC counts are only slightly higher than the normal noise level; however, the waveform shape is the primary concern. And why its only observed in one channel as both channels have same configurations?https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1643093/lmx2695sepevm-is-there-a-datasheet-available-for-the-lmx2624-lmx2695-sepWed, 06 May 2026 13:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9ea2e02b-f9d0-4f02-979b-e83441ceec4dken masonPart Number: LMX2695SEPEVM Other Parts Discussed in Thread: LMX2624-SP , LMX2695-SEP , LMX2595 In the 2026 TI Space Products Guide there is mention of the LMX2624-SP & LMX2695-SEP (page 16). I can find the LMX2624-SP datasheet but not the LMX2695-SEP, what is the difference? How does the LMX2695-SEP differ from the LMX2595, is there any radiation data on the LMX2595?LMX2624-SPLMX2595LMX2695-SEPLMX2695SEPEVMhttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1629534/afe7900-nco-phase-accumulator-reset-after-freq-change/6334720Wed, 06 May 2026 13:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4bb2dcb8-8fc9-4aad-b034-7e97dfe026f1arye nudelmanHi do you have any answer?https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1642852/afe7950evm-unable-to-program-afeWed, 06 May 2026 05:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:806b3fe5-5e90-441b-92fa-34ca8ab86613Varshini NarayanaPart Number: AFE7950EVM Other Parts Discussed in Thread: AFE7900 , LMK04828 I have pasted LMKProgram.py program. My issue will be written in next point.(Note: LMK is getting programmed and I am getting qpll acknowledgement) I am trying to program Afe but i am getting follwoing errors (AFE is not getting programmed) #====== #Executing .. AFE7900/NDET_7900/program_AFE.py #Start Time 2026-05-06 10:43:04.027000 The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 LMK and FPGA Configured. DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x11 AFE Reset Done Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error AFE MCU Wake up done and patch loaded. PLL Locked AFE PLL Configured. AFE SerDes Configured. AFE Digital Chains configured. AFE TX Analog configured. AFE RX Analog configured. AFE FB Analog configured. AFE JESD configured. AFE AGC configured. AFE GPIO configured. Sysref Read as expected ###########Device DAC JESD-RX 0 Link Status########### Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 0; Alarms: 0x0 ################################### ###########Device DAC JESD-RX 1 Link Status########### Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 1; Alarms: 0x0 ################################### AFE Configuration Complete #Done executing .. AFE7900/NDET_7900/program_AFE.py #End Time 2026-05-06 10:44:53.156000 #Execution Time = 109.128999949 s #================ ERRORS:10, WARNINGS:0 ================# #================ LMK Program ================# ''' Validation : AFE79xx Library Version v1.67, v1.74 Case RX TX FB CLK Notes ---- ----------------- ----------------- ----------------- ----------- ------------ 1 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in interleaved mode SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M 2 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in straight mode SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M ''' setupParams.skipFpga = 1 sysParams = AFE.systemParams setupParams.fpgaRefClk = 245.76#184.32# AFE.systemStatus.loadTrims = 1 sysParams.fbEnable = [False]*2 sysParams.externalClockTx = False sysParams.externalClockRx = False sysParams.FRef = 491.52 sysParams.FadcRx = 2949.12 sysParams.FadcFb = 2949.12 sysParams.Fdac = 2949.12*4 sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs sysParams.modeTdd = 0 # 0- Single TDD Pin for all Channels # 1- Separate Control for 2T/2R/1F # 2- Separate Control for 1T/1R/1F sysParams.RRFMode = 0 #4T4R2F FDD mode sysParams.jesdSystemMode = [3,3] #SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb #SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb #SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2 #SystemMode 3: 1R ; rx1-rx1-rx1-rx1 #SystemMode 4: 1F ; fb-fb-fb-fb #SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb #SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1 sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback sysParams.LMFSHdRx = ["44210","44210","44210","44210"] # The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd. sysParams.LMFSHdFb = ["22210","22210"] sysParams.LMFSHdTx = ["44210","44210","44210","44210"] sysParams.jesdTxProtocol = [0,0] sysParams.jesdRxProtocol = [0,0] sysParams.serdesFirmware = True # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location. # Note that across 2T Mux is not possible in 0.5. # For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]] sysParams.serdesTxLanePolarity = [True, True, False, False, True, True, False, False] sysParams.jesdRxLaneMux = [0,1,2,3,4,5,7,6] #[0,1,2,3,4,5,7,6] # Enter which lanes you want in each location. # Note that across 2R Mux is not possible in 0.5. # For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]] sysParams.serdesRxLanePolarity = [True, True, True, True, False, False, False, False] sysParams.jesdRxRbd = [4, 4] sysParams.rxJesdTxScr = [False]*4 sysParams.fbJesdTxScr = [False]*2 sysParams.jesdRxScr = [False]*4 sysParams.rxJesdTxK = [32]*4 sysParams.fbJesdTxK = [32]*2 sysParams.jesdRxK = [16]*4 sysParams.ncoFreqMode = "FCW" sysParams.txNco0 = [[3800,1800], #Band0, Band1 for TxA for NCO0 [1000,1800], #Band0, Band1 for TxB for NCO0 [3800,1800], #Band0, Band1 for TxC for NCO0 [1800,1800]] #Band0, Band1 for TxD for NCO0 sysParams.rxNco0 = [[3800,1800], #Band0, Band1 for RxA for NCO0 [1000,1800], #Band0, Band1 for RxB for NCO0 [3800,1800], #Band0, Band1 for RxC foQr NCO0 [1800,1800]] #Band0, Band1 for RxD for NCO0 sysParams.fbNco0 = [1800,1800] #FBA, FBC for NCO0 sysParams.fbNco1 = [1800,1800] #FBA, FBC for NCO1 sysParams.fbNco2 = [1800,1800] #FBA, FBC for NCO2 sysParams.fbNco3 = [1800,1800] #FBA, FBC for NCO3 sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual sysParams.numBandsFb = [0,0] sysParams.numBandsTx = [0,0,0,0] sysParams.ddcFactorRx = [6]*4 # DDC decimation factor for RX A, B, C and D sysParams.ddcFactorFb = [6]*4 sysParams.ducFactorTx = [24]*4 ## The following parameters sets up the LMK04828 clocking schemes lmkParams.pllEn = True#False#False lmkParams.inputClk = 1474.56#737.28 lmkParams.sysrefFreq = 2949.12/1024 lmkParams.lmkFrefClk = True ## The following parameters sets up the register and macro dumps logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt") #lmklogDumpInst = mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxpg1.txt") logDumpInst.logFormat = 0x21 #logDumpInst.logFormat = 0x0f logDumpInst.rewriteFile = 1 lmk.logClassInst =logDumpInst logDumpInst.rewriteFileFormat4 = 1 device.optimizeWrites = 0 device.rawWriteLogEn = 1 lmk.rawWriteLogEn = 1 ## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57 sysParams.jesdABLvdsSync = 0 sysParams.jesdCDLvdsSync = 0 sysParams.rxJesdTxSyncMux = [0,0,0,0] sysParams.fbJesdTxSyncMux = [0,0] sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1] sysParams.syncLoopBack = True sysParams.defaultRxDsa =[0,0,0,0] sysParams.defaultFbDsa = [0,0] sysParams.defaultTxDsa =[0,0,0,0] # ## The following parameters sets up the AGC # sysParams.agcParams[0].agcMode = 1 ##internal AGC # sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector # sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack # sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay # sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB # sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB # sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold # sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold # sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. # sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant # sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock # sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock # sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC # sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC # sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation # sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0 # sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required. # sysParams.agcParams[0].alcEn = 1 # sysParams.agcParams[0].alcMode = 0 ##floating point DGC # sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB # sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent ## The following parameters sets up the GPIOs sysParams.gpioMapping={ 'H8': 'ADC_SYNC0', 'H7': 'DAC_SYNC0', 'N8': 'ADC_SYNC2', 'N7': 'ADC_SYNC3', 'H9': 'ADC_SYNC1', 'G9': 'DAC_SYNC1', 'N9': 'DAC_SYNC2', 'P9': 'DAC_SYNC3', 'P14': 'GLOBAL_PDN', 'K14': 'FBABTDD', 'R6': 'FBCDTDD', 'H15': ['TXATDD','TXBTDD'], 'V5': ['TXCTDD','TXDTDD'], 'E7': ['RXATDD','RXBTDD'], 'R15': ['RXCTDD','RXDTDD']} #AFE.systemParams.papParams[0]['enable'] = True #AFE.systemParams.papParams[1]['enable'] = True #AFE.systemParams.papParams[2]['enable'] = True #AFE.systemParams.papParams[3]['enable'] = True setupParams.skipLmk = False AFE.initializeConfig() lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq lmkParams.lmkPulseSysrefMode = False AFE.LMK.lmkConfig()LMK04828AFE7950EVMAerospace & DefenseAFE7900https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1642700/afe7900-custom-hardware-minimal-ftdi-latte-interface-requirements/6333692Tue, 05 May 2026 21:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ce839b30-5318-470b-89b4-bc2801e592eaDavid ChaparroHi Tobias, Please see my responses below. CPLD usage on the EVM The CPLD is not used on our EVMs. This is not needed and can be ignored/removed. FTDI JTAG connection to the AFE7900 Latte does not use the JTAG port to configure the device so this is not needed for bringup. JTAG is only used for boundary scan. FTDI EEPROM contents / identification The FTDI EEPROM is programmed with a descriptor, AFE79xx HSC1386, that the Latte SW is expecting. If you were to use the module you could upload the same descriptor, and assuming the pins are in the same order, and have Latte access the devices. Minimal interface for custom hardware For a custom AFE7900 board that should initially be configurable from Latte, would the following interface be sufficient? FTDI channel for AFE SPIA FTDI channel for LMK SPI Reset control for the AFE7900 optional UART/debug connection no AFE JTAG no CPLD SPI, assuming no CPLD is used on the custom board Yes, the above interface connections would be sufficient. Regards, David Chaparrohttps://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1642762/afe7950-restricted-data-sheetTue, 05 May 2026 20:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d15b8299-76c3-4266-9778-2cb7d1e832fbLauren WatkinsPart Number: AFE7950 Please send information on the serial interface to the AFE7950 converter and the serial chip - to include layoutAFE7950https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1642761/afe7950-data-sheet-restrictedTue, 05 May 2026 20:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0ab3b637-4919-4235-b1f6-1b88d5c6efd5Lauren WatkinsPart Number: AFE7950 I am looking for information on the serial interface and overflow flag for the AFE7950 A/D. The deveice is designed into a product and we need to make modification to the productAFE7950https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1642720/afe7950-ti-jesd204-ip-3-rx-and-2-tx-mapped-to-one-amd-quad-transceiverTue, 05 May 2026 17:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:351e6f86-d742-4989-a074-5f85a422b902Scott GeaghanPart Number: AFE7950 Hello, I’m using your TI-JESD204c IP on a Versal VCK190 Evaluation Platform. I have a configuration with 3 RX lanes and 2 TX lanes. All lanes run at a line rate of 24.75 Gb/sec with 64b66b encoding. All lanes use a reference clock of 375 MHz. I need to map the design to a single quad transceiver on the FPGA. This configuration maps to what we believe to be a valid operating mode on the TI AFE7950. Everything works in QuestaSim if I use the following configuration: 1. One instantiation of the TI IP configured for simplex TX with 2 lanes 2. One instantiation of the TI IP configured for simplex RX with 3 lanes 3. One instantiation of the TI IP configured for simplex RX with 2 lanes (simulation only, connects to #1) 4. One instantiation of the TI IP configured for simplex TX with 3 lanes (simulation only, connects to #2) #1 and #2 need to synthesize, and #3 and #4 are for simulation only. #1, #2, #3, and #4 are all separate TI IP simplex instantiations that use separate simplex instantiations of the Versal transceiver IP. I can build an FPGA with #1 and #2, but Vivado won’t let me map #1 and #2 to the same quad transceiver, which is a requirement for my company. I created a new Versal transceiver that contains two interfaces. Interface zero is simplex RX with 3 lanes. Interface one is simplex TX with 2 lanes. In other words, I combined #1 and #2 into one Versal transceiver instantiation. Let’s call this the duplex instantiation with asymmetrical TX (2 lanes) and RX (3 lanes). It is my understanding that creating one Versal transceiver with one simplex RX interface (3 lanes) and one simplex TX interface (2 lanes), all using the same line rate and reference clock rate, will allow me to map the transceiver to a single quad transceiver on the FPGA. I’m still instantiating #3 and #4 for simulation. When I simulate the duplex transceiver, the duplex receiver locks on the 3 RX lanes and receives data. However, #3 never locks on the 2 RX lanes. Can you please help me get this working? One thing that confuses me is that your Verilog header file (jesd_link_params.vh) allows one to define NUMBER_OF_RX_LANES and NUMBER_OF_TX_LANES. I would like NUMBER_OF_RX_LANES to be 3 and NUMBER_OF_TX_LANES to be 2. However, your wrapper module (mgt_64b66b_wrap) only defines NUM_LANES. I want to instantiate a Versal transceiver inside mgt_64b66b_wrap() that has (NUMBER_OF_RX_LANES == 3) and (NUMBER_OF_TX_LANES == 2). Can this be done? If not, is there some other way to accomplish what I need to do? Regards, Scott Geaghan Assurance Technology CorporationTI-JESD204-IPAFE7950https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1642700/afe7900-custom-hardware-minimal-ftdi-latte-interface-requirementsTue, 05 May 2026 16:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5beb61af-0fe3-4457-8926-3765c2c7d61eRenan Santos AdrianoPart Number: AFE7900 Hello Experts, I am designing custom hardware (Software Defined Radio) using the AFE7900. For the first development phase, I would like to configure the AFE7900 and the LMK clocking device directly from Latte, similar to the AFE7900EVM flow. I reviewed the AFE7900EVM schematic and noticed that the onboard FT4232H connects to several interfaces, including AFE SPIA, additional SPI interfaces, UART, CPLD SPI, I2C, and an AFE JTAG connection. I would like to simplify this on my custom board and only keep the interfaces required for Latte-based configuration. My current understanding is that Latte mainly needs: AFE SPIA LMK SPI AFE reset optionally UART for FPGA/debug purposes I have the following questions: CPLD usage on the EVM Is the CPLD actually required by Latte during normal AFE7900 and LMK configuration? From my current analysis, it looks like the CPLD on the EVM is not required for the basic Latte configuration flow, but I would like to confirm this. FTDI JTAG connection to the AFE7900 The EVM routes one FT4232H channel to the AFE JTAG pins. Is this JTAG interface used by Latte when configuring the AFE7900, loading patches, or initializing the device? Or is it only intended for TI internal debug, boundary scan, or factory/test purposes? FTDI EEPROM contents / identification What exactly is programmed into the FTDI EEPROM on the AFE7900EVM (U12)? Does Latte depend on a specific EEPROM configuration, such as product description, serial number, channel mode, or FTDI interface assignment? Can I use a standard FTDI module, for example the FT4232H-56Q MINI MDL, for Latte access if it has the same EEPROM device, or does it need to be programmed with EVM-specific contents? Minimal interface for custom hardware For a custom AFE7900 board that should initially be configurable from Latte, would the following interface be sufficient? FTDI channel for AFE SPIA FTDI channel for LMK SPI Reset control for the AFE7900 optional UART/debug connection no AFE JTAG no CPLD SPI, assuming no CPLD is used on the custom board Could you please confirm the minimum required FTDI/Latte interface for custom hardware? The goal is to keep the custom PCB as simple as possible while still being able to use Latte during early bring-up and development. Best regards, TobiasAFE7900EVMAFE7900