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Part Number: ADC32RF80
We have a block ADC32RF80EVM development board for use with the TSW14J56EVM. There are a few questions:
1. ADC32RF80 is 14 bits, the peak-to-peak value is 1.3V, and the full-scale count is 16384. But to use DDC, I set the 16-bit NCO frequency to 0, then one signal I is multiplied by 1, and the other Q is multiplied by 0. The output data I is 16-bit signals, the full-scale count bit is 65536, and the other Q is 0. I want to know how the 16-bit data corresponds to the 14-bit ADC data. 14-bit data is multiplied by 16-bit 1 and the highest two bits should be It is 0, the full scale should be 16384, how is it 65536? and When I input a signal with vpp=0.95V, the ADC sample data is almost 65536？
2. If i select the complex output, I is the signal, Q is 0. If you choose the real output, the output signal is not what I want, how is the complex to real module converted?
3. If it is fs=3Ghz, Divide-by-4 complex, Figure 97 shows the bandwidth 0.1*FS=300Mhz in adc32rf80.pdf, and OUTPUT BANDWIDTH (MHz) PER BAND is 600Mhz in Table 4. Why is it different? What is the meaning of the second bandwidth?
1. The 14-bit output from the ADC's quantizer is down-converted digitally where the other (NCO) input into the down-converter is 16-bits. Therefore, rest of the digital signal path operates at 16-bit resolution.
2. This is illustrated in figure 93 of the device datasheet.
3. The 600MHz BW is complex. figure 97 shows the BW for either I or Q.
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In reply to Satish Uppathil:
thanks for the reply
What I don't understand is how the 16-bit data corresponds to the input amplitude. The ADC32RF80 input signal Vpp = 1.3V, but when the input signal Vpp = 0.95V, the output data is almost 65536. For example, when the NCO frequency is 0, the ADC data is 16384, does the corresponding 16-bit data be 65536?
In reply to chi zhang2:
The FS at the input should result in 16-bits max code at the output. This device doesn't support bypass mode and so, you'll have to set an NCO in addition to the decimation ratio.
I have asked for more details from the development team and I'll get back to you.
When the NCO is set to Zero, the signal path will reduce to a simple real decimation chain. In this case, the multiplication by 2 in the last decimation stage needs to be disabled.
Two Scenarios of operating mode:
1. Normal (non-zero) NCO: Here real input is converted to a complex base-band output. In this case, the last stage multiplication by 2 has to be enabled to ensure full scale real tone at ADC output maps to a full scale complex base-band tone at DDC output.
2. Zero NCO: DDC reduces to a simple real decimation chain (Only I output will be non-zero). In this case the last stage multiplication by 2 has to be disabled to ensure full scale ADC output maps to full scale DDC output.
You're seeing a full-scale output at lower input as this stage (multiplication by 2) is not getting disabled.
Thanks for the reply, there is another question, where to set the last stage multiplication by 2
you can do that with a register write. highlighted below is the relevant register.
Thank you very much for solving my problem
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