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DAC38RF82: SerDes PLL cannot locked

Prodigy 130 points

Replies: 15

Views: 346

Part Number: DAC38RF82

Hi Jim,

  I cannot get  SerDes PLL to lock when I use the DAC38RF82. I have checked all supply voltages, grounds, and they seem ok.

The DAC PLL REFCLK is 450MHz, DAC PLL output is 9GHz, use mode 82121,2TX, 8X,JESD lane rate 11.25Gbps.

The SerDes PLL register configuration :

Address      Data

0x43B          0x9802

0x43C          0x8029

0x43D          0x0088

0x43E          0x0929

0x43F          0x0000

  I also set LANE_ENA to 1(0x14A 0x0f03,0x24A 0xf003). The register 0x05[1:2] on page 0 is "11" that means the SerDes PLL is unlocked. To verify, I set ENDIVCLK to produce a SERDES PLL output divided by 80

on the ALARM pin. I do not see any clock on the ALARM pin. It seems the SerDes PLL VCO is not work. Can you help me debug this issue?

Regards,

Tang

  • Guru 66160 points

    Tang,

    Did you perform a PLL Auto tune function? You must do this to lock the DAC PLL. What value do you read in address 0x06? This is the PLL LF voltage register and the value needs to be either 3 or 4. What value is the VCO tune (address 0x433)?

    Regards,

    Jim

  • In reply to jim s:

    Hi Jim,

    The DAC PLL is locked,and the 0x06 is 0x3F62. On a subsequent test, I find that the Serdes 0 block goes out of lock but the Serdes 1 block is locked.

    I find it has an NCO ONLY mode, how to implement this functionality?

    Regards,

    tang

  • Guru 66160 points

    In reply to user6236564:

    DAC38RF82_NCO_Only_Test.pptxBoard trouble-shooting tips.docxTang,

    See if these documents help.

    Regards,

    Jim

     

  • In reply to jim s:

    Hi Jim,

    Thank you for your support. 

    I have tested what list in the document, and they all passed by. The JESD is ready( SYNC going low to high, 0x64-0x6B all are '0x0000', 0x04 is '0x0000'), but there is no output signal.

    Are there any other registers that may cause this problem?

    Thanks,

    Tang

  • Guru 66160 points

    In reply to user6236564:

    82121_9G_450M_ref.cfgTang,

    Verify your DAC register settings with the ones attached. With your setup from an earlier post, you need to change your interpolation from 8x to 4x. 8x is not an option with this setup.

    Regards,

    Jim,

  • In reply to jim s:

    Hi,Jim

    I  test register settings that you offered. I find Sync signal always from High to low which mean errors cause  sync requests. I read register 0x64-0x6B, they are all '0x9702'. I am compared with JESD Alarms for Lane Register, it says that bit 15 = multiframe alignment error, bit 11 = elastic buffer over flow(bad RBD value), bit 10 = code synchronization error, bit 9 = 8b/10b disparity error, bit 8 = 8b/10b disparity error.

    In the register setting, K is 20 and RBD is 19. And I try to reduce the value of RBD(17 or 18), the error of bad RBD value is always existe. I don't know how to resolve those problems, can you give me some advice?

    I also find when I set the register 0x410 to '0x0001', errors do not cause sync requests. There is quite a lack of information about the register 0x410 in the data sheet, could you give me some more details about register 0x410,0x411,0x412?

    Best Regards,

    tang

  • Guru 66160 points

    In reply to user6236564:

    Tang,

    You may have to change a few registers setting in the file I sent before you can use it with your system. The lanes may be mapped wrong, the clock selection (single-ended vs differential) may be set wrong, the VCO Tune value may be incorrect, the K value may not match your transmitter's K value, ect...

    Registers 0x410 and 0x411 are alarms that could occur if the internal clock divider is not operating properly. If this is the case, there are usually many other issues and alarms that will be present. I would not worry about monitoring these two registers as they really will not provide much information.

    Register 0x412 is a skew counter that increments +1 for every 2 octets processed. This logic will reset when receiving data from the earliest lane then stop counting when it gets data from the latest lane.

    You mentioned in an earlier post SYNC was working properly but there was no output. In your latest post, you are mentioning SYNC is staying low. What did you change to cause this? Was this from using the configuration file I sent?

    What FPGA are using to provide data to the DAC?

    Regards,

    Jim

     

  • In reply to jim s:

    Jim,

    I'm sorry to reply you so late. Because of the Spring Festival and Pneumonia Virus Outbreak in China, I haven't been to work recently.

    No, I compared the configuration file which you sent me with register configuration I used, I found it almost the same,except the clock selection (single-ended vs differential), the VCO Tune value, the K value, Lane map. These need to be configured according to my actual situation,so I do not change my register configuration.

    At first, SYNC seemed to be working properly and there was no output. Then I found that I made a mistake. I set the register 0x410 to '0x0001', but the recommendation is ‘0x0000’. After I corrected that mistake,SYNC was staying low and sync signal always requests resynchronization. That's why I wonder if register 0x410 has some other functions.

    I use XC7VX330T-3FFG to provide data to the DAC. I've used this FPGA before, and It supports JESD transmission protocols.

    Regards,

    tang

  • Guru 66160 points

    In reply to user6236564:

    Tang,

    Send me you latest config file. Please also send the following info:

    DAC sample rate

    External DAC clock or PLL. If PLL, reference clock frequency and N and M values used by PLL.

    IQ or real data. If IQ data, 1 pair or 2.

    interpolation factor

    LMFS settings

    RBD setting

    K setting

    SYSREF frequency

    I will make the required changes the try your settings on our hardware.

    Regards,

    Jim

  • In reply to jim s:

    Jim,

    Thank you for your help. That would be very useful.

    DAC sample rate is 9GHz

    Use PLL, the reference clock frequency is 450MHz, N=1, M=5

    Real data input

    Interpolation factor is 4X

    LMFS is 8212

    RBD is 19

    K is 20

    SYSREF frequency is 28.125MHz

    Table1 is my register setting and configuration of sequence. I also make register setting TXT file, It may be more convenient for you to use.

    Regards,

    tang

    1)5102.latest config file.docx

    2)7713.latest config file.txt

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