Hi Jim,
I cannot get SerDes PLL to lock when I use the DAC38RF82. I have checked all supply voltages, grounds, and they seem ok.
The DAC PLL REFCLK is 450MHz, DAC PLL output is 9GHz, use mode 82121,2TX, 8X,JESD lane rate 11.25Gbps.
The SerDes PLL register configuration :
Address Data
0x43B 0x9802
0x43C 0x8029
0x43D 0x0088
0x43E 0x0929
0x43F 0x0000
I also set LANE_ENA to 1(0x14A 0x0f03,0x24A 0xf003). The register 0x05[1:2] on page 0 is "11" that means the SerDes PLL is unlocked. To verify, I set ENDIVCLK to produce a SERDES PLL output divided by 80
on the ALARM pin. I do not see any clock on the ALARM pin. It seems the SerDes PLL VCO is not work. Can you help me debug this issue?
Regards,
Tang