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DAC38RF80: Length matching requirements between data lanes of 3 DACs for synchronization

LALIT VERMA
Expert 1635 points
Part Number: DAC38RF80

Hi,

We are using three DAC38RF80 in our design. We need synchronization between three DACs and also deterministic latency.

So I want to know  the length matching requirements (in mils or ps) between: 

1. Data lanes of all three DACs coming from single FPGA through FMC connector.

2. DEVLCK and SYSREF going to three DACs and FPGA.

Also does SYNC going from DACs to FPGA needs to be length matched with any clock (DEVCLK or SYSREF) going to FPGA?

An early response will be highly appreciated.

Thanks,

Lalit

  • 0
    TI__Genius 9695 points

    Hi Lalit,

    You can refer to the layout reference below.

    For the serdes, keeping the lane to lane skew under 320ps is a good rule of thumb.

    SYSREF and device clock should be length matched, as close as possible to be under 10mils

    For SYNC, I will advice you to combine the SYNCs from all 3 DACs into a single SYNC with an AND gate. The skew between SYNC will not matter if you combine them. Otherwise, the skew should be under 1 LMFC period

    Thanks,

    Eben.

  • 0 in reply to Ebenezer Dwobeng
    Expert 1635 points

    Hi Eben,

    Thanks for the useful information.

    I have one more question for you.

    Does SYNC from DAC also need to length match with clocks (SYSREF,DEVCLK) going to FPGA.

    Thanks,

    Lalit

  • 0 in reply to LALIT VERMA
    TI__Guru 66104 points

    Hi Lalit,

    The DAC38RF80 is subclass 1 device and should not be sensitive to SYNC~ line skew. You may refer to section 4.12 of the JESD204B document for detail. The JESD204B document is available on JEDEC website free of charge. TI is not allow to distribute this directly to you. thanks.

    -Kang