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Part Number: DAC38RF83
When debugging DAC38RF83, we find that there are several error report.
one of them is Link configuration error which can re-triger a SYNC~.
Link configuration error =TX and RX parameters do not match
Can you elabrate which kind of parameters will be match?
I know that L-M-F-S-K-HD-N must be met. Other parameter such as BID/ DID /Lane ID /CS must be met?
Since L-M-F-S-K-HD-N have already met between the link partners, there is still such "Link configuration error" and we are confused.
You may ignore the link configuration parameter in the DAC bring-up by going to the SYNC_REQUEST register and write the link configuration check bit (bit 5) to 0. This will allow the JESD204 RX state machine to ignore the ILAS sequence and continue to finish the link establishment.
Here is an example ILAS for DAC38j84 with similar JESD204 implementation as the DAC38RF83. The ILAS is programmable in the DAC registers. There are checksum value for the ILAS that also need to be met.
I typically think ILAS is not critical for link establishment. It is just a protocol to ensure the TX and RX device would match. As you can see, it definitely complicates the bring-up process, therefore, most of our customers just choose to ignore the ILAS check
DAC3xJ8x ILA Sequence.xlsx
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In reply to Kang Hsia:
Thank you for your professional answer.
I do believe that ILAS parameter is not critical for link establishment. I have used many other DAC with JESD204B interface .Almost all of them
ignore the TX's parameter send during ILAS. But I find that DAC38RF83 indeed check the parameters. Recently, I find that those parameters influence
my link establishment.
I will try it as your suggestion soon.
In reply to XiaoTao Ng:
I agree with your assessment.
My TX side repeatly send out K28.7 for lane sync when the L-M-F-S-Hd= 82121
The handshake character should be K28.5 or 0xBCBC characters. The K28.7 character is for frame alignment. This may mean your FPGA is not initialized correctly. Please double confirm if you can reset your FPGA JESD IP to have it send out K28.5 for handshake in CGS mode.
May my description is misleading. It doesn't means that K28.7 was send always.
JESD TX side have finished CGS and ILAS,during the USERDATA phase ,the K28.7.mentioned is the JESD204B.01 STANDARD chapter <<18.104.22.168.2Character replacement without scrambling>> .
The JESD RX receiver on the DAC is checking for the k28.7 character in the character replacement for proper alignment of frame. A frame boundary is defined to "F", which is 1 in your case. This mean F = 1 octet per frame.
The fact that you see SYNC request or SYNC toggle low upon K28.7 character potentially indicates the JESD TX on your FPGA side has "drifting" or "unlocked" frame boundary with respect to the DAC. We have seen cases where customers did not initialize the FPGA IP correctly and such behavior happens. Also, if the FPGA and DAC have unlocked reference clock, such behavior shows up.
In the SYNC REQUEST register, simply set Frame Alignment Check to 0, and see if the issue can be improved.
May problems comes from TX side . I have make some changes and taken some optimizations in system.
When DAC ‘s register 0x51@page 1 = 0x00DF | 0x51@page 1 = 0x00DF
SYNC~ monitored by TX side in FPGA always keep high . SYNC~ flipping never happens.
good to know. Yes, please check your FPGA frame alignment and character insertion capabilities in your JEDS204 IP
In my opoinion, The fact that SYNC~ always keep high means the JESD204B link has been established successfully.(DAC ‘s register 0x51@page 1 = 0x00DF | 0x51@page 1 = 0x00DF)
So I generated a test tone in FPGA and send them to DAC. DAC output nothing.
DAC has some flags can be readback to make sure that the link is ok ?
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