Part Number: DAC38RF89
Hi,My customer occurred JESD error. Could you please answer his questions?
Error is shown on JESD_ALM_L[0:7] registers as follows:
JESD_ALM_L0 0x2000JESD_ALM_L1 0x2F00JESD_ALM_L2 0x2000JESD_ALM_L3 0x2800JESD_ALM_L4 0x2800JESD_ALM_L5 0x2000JESD_ALM_L6 0x2800JESD_ALM_L7 0x2800
When DAC output Zero, he has not observed issue yet. However, when actual data is output, issue is happened. There is this issue on only one board out of 16 boards.
Please advise us.
Thanks and best regards,M.HATTORI
The first step is to resolve code group synchronization. There is code group synchronization error which means K28.5 characters were not detected properly. The customer may probe during link-up to see if there are 0xBCBC or k28.5 during hand-shake.
Please ensure there are proper positive/negative routing of the SerDes lane from FPGA to the DAC SRX input.
I will send you some documents offline to review with the customer.
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In reply to Kang Hsia:
Just checking for your response.
Hi,Sorry for late response. This error is occurred on once per 10 times power-up.
Please tell us the setting procedure at startup and the settings to be checked such as the equalizer setting.
Also, the SRDS_CFG1,2 registers, etc. have been changed. Is it necessary to initialize the JESD circuit after the changes?(Bit1, 0 of RESET_CONFIG register, INIT_SLICE 1 → 0 etc.)
Thanks and best regards,M.HATTORI.
In reply to Motoyasu Hattori:
The SerDes is adaptive and should not need further configuration after initial link training. I will take a closer look and get back to you.
Please see below report for some debug strategies.
whenever serdes block have been changed, we recommend performing another init on the init_Slice to reset the JESD204 core.
General Alarms for All Converters.pptx
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