DAC38RF80: DAC38RF80: single link driving both DAC channels.
Part Number: DAC38RF80
We are planning to use multiple DAC38RF80. I've read thru datasheet sections 8.3.9, 8.3.10 on the multi-Device synchronization. How does that work when the DUC and internal DAC clock PLL are used. It appears the DUC can be synchronized using SYSREF, but I don't see a detailed explanation of how it works. Also, how is the internal PLL synchronized, in order to repeatably phase align its output. Note: for our application, the SYSREF signal and lower frequency input DACCLK signal (~250MHz) will be generated by using a high quality JESD204B clock generator. We'll be using 8x or 12x interpolation in the DAC38RF80, and the internal DAC clock will be minimum of 6GHz. thanks,Scott
The attached documents all have some information regarding what you are trying to do. The key to getting this to work will be through the use of the SYNC signal, SYSREF, PLL dividers used, and NCO frequency with respect to the SYSREF frequency.
More information regarding the use of the LMK family of parts to provide an option for a clocking solution can be requested on the high speed clocking forum.
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In reply to jim s:
Jim, Thank you for the info. For our application, there are several options for selecting the DAC38RF8x's Device Clock: 1) use the Device clock directly as the DAC sampling clock, or 2) as a reference clock that is multiplied up by internal PLL to generate the sampling clock. How do we quantify each in terms of the accuracy and repeatability of their output phase alignment across multiple devices? Since we are in the process of designing a custom transmitter, we have latitude to select the best option. We're planning to use a LMK0428x (or equivalent) to generate the device clocks and SYSREFs; our input IQ data rate to the DAC is 750 MSPS using 4 serdes lanes running at 7.5Gbps. We'll be interpolating and shifting up the IQ data to around 1 GHz center frequency using the DUC. Our interpolation rate can be 4x to 12x, where higher is preferred for moving the DAC image further out. As far as device clock rate, we can generated low jitter clock rates upto 3 GHz, including integer division rates at 1500, 750, 500, ... MHz. To help meet the DAC's setup & hold requirements, we can tightly control the length matching of the device clocks and SYSREF signals going to the DAC, as well as add delay to the clock and/or SYSREF within the clock generator. For option 1), the device clock = DAC sampling clock = 3 GSPS. The internal PLL is disabled. This assumes 4x interpolation can be done using the DAC38RF82. Note: its datasheet says it supports 4x interpolation, but doesn't say if its works at 3 GSPS. Also, the DAC38RF8x EVM GUI doesn't list 4x as an option for DAC38RF82. There is no internal PLL to synchronized, but the interpolation filters (with input rate of 750 MSPS) and NCO must be synchronized across devices. Is this option feasible? For option 2), the device clock can be set to 3000, 1500, 750, 500, ... MHz. The DAC sampling clock is generated using the internal PLL. 8x or 12x interpolation can be used, with DAC sampling clock rates of 6 or 9 GSPS, respectively. If the Device Clock is 500MHz or less, we could avoid the 'divide by N' block synchronization between the reference clock & PFD block. Does this help simplify the synchronization, and improve alignment?Thanks.Scott
In reply to Scott Greeley1:
The DAC38RF82 does support 4x interpolation, but to use this you can only use a real input and not IQ pairs. Furthermore, with the real input you are limited to 1x, 2x, and 4x interpolation. This may make this option not feasible if you are trying to use 4x interpolation and IQ data.
Option 2 and using the internal PLL could greatly help synchronization as you would be able to use a lower frequency SYSREF which would help with the setup and hold requirements.
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