Other Parts Discussed in Thread: LMK04828,
Hi everyone,
I am currently trying to understand the reference design KCU105 AFE74xx XCVR 2x44210 JESD. I would like to understand the JESD mode 2x44210 as mentioned in the reference design user guide. I looked at different documents regarding what the L-M-S-F meant and got more confused than able to understand them clearly. I referred to the following sources and tried to collaborate the understanding with the FPGA block diagram provided in the reference design.
The definitions for L-M-F-S varied in both the sources and I could not make sense anymore.
I wanted the SerDes line rate 7.3728 Gbps and hence looked at the mode corresponding to that in 'AFE74xxEVM User's Guide' and found the following table
Then from the following table
Can someone clarify what the following terms are, in the FPGA block diagram and also with other illustrations if possible
1) Converters
2) Lanes
3) Number of frames for a particular mode (2x44210 here)
Basically the whole L-M-F-S part
Thanks in advance,
-Chandrasekhar DVS