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AFE7444: IP support for the reference design KCU105 AFE74xx XCVR 2x44210 to replicate on Vivado 2018.2

Genius 3040 points

Replies: 25

Views: 530

Part Number: AFE7444

Hi everyone,

I am currently studying the reference design KCU105 AFE74xx XCVR 2x44210. The reference Vivado project is implemented on Vivado v2016.1. However I would like to port it to Vivado v2018.2 and started building the block design from scratch. I see some of the IPs are not present in the IP repository of Vivado v2018.2.

After searching through reference design, I was able to add the following IPs in Vivado v2018.2, by adding the path of repository directory 'repository_0' from the reference design.

1.iobufs_ti_v1_0
2.leds_v1_0

However, the following IP (source) is still missing

1.transport_layer_afe768x_44210_0

Does ti provide support for this? How can I obtain this IP so I can complete re-building the block design on Vivado 2018.2?

Can someone help me with this?

Thanks in advance,

-Chandrasekhar DVS

  • Hi Chandrasekhar,

    The verilog file is located at below location on the PC where KCU105 firmware is unpacked: 

    C:\Program Files (x86)\Texas Instruments\KCU105 Firmware\AFE74xx XCVR 2x44210\Source Code\KCU105_AFE74xx_XCVR_2x44210_7p3728G\KCU105_AFE74xx_XCVR_2x44210_7p3728G\prj_MyKcu105_TI.srcs\sources_1\new\transport_layer_afe768x_44210.v

    This file can be added to your v2018.2 project.

    Reference design is given in Vivado version 2016 as a reference starting point for FPGA development. Unfortunately, TI can not provide reference designs in different versions of Vivado.

    Regards,

    Vijay

  • In reply to Vijayendra Varma Siddamsetty:

    Hi Vijay,

    So I would like to atleast obtain the IP project for 'transport_layer_afe768x_44210_0'  IP in the block design. In the reference design, it is locked. With an unlocked custom IP, it is possible to upgrade it, so as to be used in Vivado 2018.2.

    Can you please provide us that module? As the Vivado environment is new to me, I would like this resource supplied.

    Thanks in advance,

    Awaiting a reply soon,

    -Chandrasekhar DVS

  • In reply to Chan100:

    Hi Chandrasekhar,

    I have contacted our firmware support team to find what we can provide to support this. Please give me until Friday to get back.

    Regards,

    Vijay

  • In reply to Vijayendra Varma Siddamsetty:

    Thanks! That would greatly help.

    -Chandrasekhar DVS

  • Guru 68700 points

    In reply to Chan100:

    Chandrasekhar,

    Please download the file from the link below. This may have what you need.

    Regards,

    Jim

    txn.box.com/.../v9u6g0qgfa01ieyukypw4qb40n418jkw

  • In reply to jim s:

    Sorry but what version of vivado was used for this? I am using vivado 2018.2. When I try to open the project, it says the project has been created with an even newer version. I might not be able to open this. 

    Can you help me here?

    Thanks in advance,

    -Chandrasekhar DVS 

  • In reply to jim s:

    Also I was using KCU105 not Zync board! I see that this project is for Zync board?

  • Guru 68700 points
  • In reply to jim s:

    Hi Jim s,

    Thanks for the reference project for 2016.1. However we already have this by filling out the form while looking at one of the afe7444 related documents. I was asking for the locked IP 'transport_layer_afe_2x44210'. This is probably because while the reference project was being created, this custom IP project path was added to the IP repository. That custom IP project is not included with the reference design that was causing 'locked IP' problems. Anyways, I was able to  create custom IP for 2018.2, simulated and tested its functionality.

    Thanks for the support,

    -Chandrasekhar DVS

  • In reply to jim s:

    Hi Jim s and Vijay,

    So I have the following things to ask regarding the reference design

    1) In the included Vivado 2016.1 project from the reference design, I see that the data output lanes from the JESD204 TX IP are not mapped to any physical pins in any of the included constraint files. Also in the implemented design, there is no automatic mapping of data output ports 'txp_out' and 'txn_out' to any physical pins(which also should not be expected as the mapping needs to be specified in a constraint file). I see that they are there for the 'rxp_in' and 'rxn_in' input ports to the top level module. Why are they not there for 'txp_out' and 'txn_out'?

    2) Based on the Encoding type (8B/10B), the JESD204B subclass two is being used in the reference design. If that were the case, the deterministic latency is determined by the SYNC~ signal (for subclass 2). Then why is SYSREF (for subclass 1) being used still?

    3) From the datasheet of AFE7444 and schematic of AFE74XXEVM , I see there are so many SYNC~ signals (syncbcmos 1- 3, ADC_SYNC, DAC_SYNC and ADC_ALT_SYNC (4+1+1+1)). Why are there so many? If it is that, there is facility to use seven independent SYNC~ signals, what are the SYNC~ used in the reference design?

    Can someone please answer the above?

    Thanks in advance,

    -Chandrasekhar DVS

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