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AFE7444EVM: Reference Design Constraints File

SM
Expert 1730 points
Part Number: AFE7444EVM

Hello,

    We are working on the AFE7444EVM with the KCU105 and hence the corresponding refrence design. There are three user constraint files in our understanding (KCU105.xdc, KCU105_io_TI.xdc, KCU105_io.xdc). 

There are lines connecting physical pins to the  the rxp lines (rxp_in[]) however the pin connections for the txp lines are not present. 

Please advise. 

  • 0
    TI__Genius 10505 points

    Hi SM,

    I have contacted our firmware support team regarding this. Please give me until Friday to get back.

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    TI__Genius 10505 points

    Hi SM,

    Here is the response I got from our firmware team:

    "Generally we don’t have to specify the SERDES line pins. These are hard blocks in the FPGA and will have a dedicated pin. So when we use the JESD IP or the Transceiver IP, Vivado knows which transceiver pins are used. It need not be specified explicitly. To verify this you may open the IO Planning window of the Synthesized design. Note the lane swap between the JESD PHY IP (jesd204_phy_0) and the JESD204 Base IP (jesd204_tx & jesd204_rx). This accounts for the lane swap between the Transceiver EVM and the KCU platform."

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Expert 1730 points

    Hello,

          With reference to the reference design, the DAC or the tx lines of the JESD interface are not connected (we checked the IO planning window of the synthesized design). This is making us weary about the reference design provided in terms of whether it will work or not. May I ask you to please have a look and provide us a fully working reference design. 

    Thanks for your support,

  • 0 in reply to SM
    TI__Genius 10505 points

    HI SM,

    Which version of Vivado are you using to open this reference design? This is a Vivado 2016.1 project. 

    Regards

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    TI__Genius 10505 points

    Hi SM,

    Here is the response I got from our firmware team:

    We have sometimes noticed that the inferred SERDES lane mapping shows up only after Implementation. Moreover, the reference design was validated to be working with the AFE74xx EVM GUI at 2x44210. You can proceed with the design without concerns. If you would prefer to have the SERDES lanes explicitly specified, you can add the attached constraints as a separate XDC or append to an existing file.”

    Note:- Between the AFE74xx EVM and the KCU105, there is SERDES lane inversion on the first four TX and RX Lanes. The AFE74xx EVM GUI inverts the TX lanes and hence this inversion is not applied in the Reference design on the TX SERDES lanes, but this is required and hence implemented on the RX Lanes.

    Regards,

    Vijay

    AFE74xx_Ref_TXLanes.zip

  • 0 in reply to Vijayendra Varma Siddamsetty
    Expert 1730 points

    Hello Vijay,

              Thank you for your input. Will study further and revert. 

    Regards,

    SM