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DAC38RF89: two DACs have phase difference.

user6193156
Intellectual 290 points
Part Number: DAC38RF89

I config DAC38RF89's JESD204B as fallowing.

It has two real input. One use DACA, the other use DACB.

When I initial DAC38RF89, the two DACs output has a phase difference,t1(two channels data is the same); if I re-initial DAC38RF89,the phase difference sometimes becomes t2 and sometimes it doesn't change.

I want to know the reason？ And how can the phase difference be fixed to 0？

  • 0
    TI__Guru* 91947 points

    User,

    All logic blocks for both paths must use the same SYNC source. This goes for the NCO registers as well. You should be operating with subclass 1 and providing at least 2 SYSREF pulses. Both DUC pages (0 and 1) should be using the same register settings for addresses 0x24, 0x27, 0x28 and 0x5C. 

    Regards,

    Jim

     

  • 0 in reply to jim s
    Intellectual 290 points

    Hi,Jim

       The register settings are:  0x24= 0x0010;0x27=0x4444;0x28=0x0440;0x5C=0x0001. The phase difference is still not fixed.

       If the  register settings change to : 0x24= 0x0010;0x27=0x2222;0x28=0x0220;0x5C=0x0001, use the sysref as the sync source,But the problem remains.

       If reset the 204B core(at the transmitter) in the FPGA and release reset,I can see the same phenomenon.

       What other reasons might lead to this problem？

    Regards，

    Su

  • 0 in reply to user6193156
    TI__Guru* 91947 points

    Su,

    Use the JESD_CROSSBAR registers (ox5F and 0x60) to swap the incoming data going to the DAC's to see if the phase difference follows the incoming data.

    Attached is the configuration file we use with our EVM using your settings. See how these register settings compare to yours. FYI, the JESD lanes are swapped around on our PCB and registers 0x5F and 0x60 settings compensate for this. 

    Regards,

    Jim

     8212_real_2x_int.cfg

  • 0 in reply to jim s
    Intellectual 290 points

    Hi,Jim,

    I use the JESD_CROSSBAR registers (ox5F and 0x60) to swap the incoming data going to the DAC's, the phase difference changes. Sometimes the phase difference changes with the input data, sometimes the phase difference is 0.

    Does this mean there is a phase difference in the input data？ Or the phase difference is generated within the DAC？

    In addition, another problem was found in the test. Sometimes the output waveform was abnormal when I swap the incoming data. 

    Regards,

    Su

  • 0 in reply to user6193156
    TI__Guru* 91947 points

    Su,

    I think the issue is with your data. You can also use the crossbar registers to send the same data to both DAC's. Try this.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 290 points

    Hi,Jim

    When I reset the FPGA 204B core, the phase difference phenomenon is very easy to appear, but if I re-initialize the jesd  of DAC(set register 0x0=0x5803,then set register 0x0=0x5800), there is no difference almost every time.

    Maybe there's something wrong with jesd synchronization？

    Should FPGA or DAC be reset first during jesd synchronization?

    Regards,

    Su

  • 0 in reply to user6193156
    TI__Guru* 91947 points

    Su,

    After you have configured the DAC registers, reset and initialize your FPGA, then follow the steps in section 9.1.1 of the DAC data sheet (Start-up Sequence).

    Regards,

    Jim