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DAC38RF82: How does 81180 mode send data in Vivado 204B corre

Prodigy 110 points

Replies: 15

Views: 381

Part Number: DAC38RF82

  • Hi Jim,

    When I use DAC38RF82, I don't know how to frame the data.

  • Regards,

    Wuge

  • Guru 67320 points

    Wuge,

    The Xilinx IP is a tad quirky when it comes to how data gets sorted, but if my understanding is correct, it will do the following:

    • The IP will have 8 lanes of 32 bits each (hence a total output of 256 bits)

    • I have illustrated the data packing in the attached document (for first 4 lanes only) for mode 81180. This applies for 8 total lanes.

    • In the next step, I have taken a 32 bit chunk and separated the data into four 8 bit packets. This is because the 8b/10b protocol works on 8bit granularity

    • As a final step, I have illustrated how the samples on Lane 0 will map to the rx_tdata[31:0] (from MSB to LSB)

    • The same mapping approach will apply to the other 7 lanes.

    Regards,

    Jim

    81180 format.xlsx

  • In reply to jim s:

    Jim,

    It has been confirmed that the group frames are ok.But I'm not sure if it's a configuration issue.When testing a single frequency signal, multiple tones are output.Attach information.test_data.txtDAC38RF8x.pdfconfig.txt

  • Guru 67320 points

    In reply to user4221793:

    Wuge,

    What is the DAC clock sample rate? What is the LMFS setting? What SYSREF frequency are you using? What is the K and RBD values? What is the interpolation factor? Is the DAC using real data or I/Q data? One I/Q per channel or two? Are you using the DAC PLL? Are you reporting an errors? Are you using the NCO?

    This info is in the config file you send but would take some time to get the info. Providing these answers will help me get back to you sooner.

    Is the data file attached what you are sending to the DAC? Please also send a screen shot of the DAC output.

    What is the group frame you are mentioning? Is the lane data sent from your FPGA?

    Regards,

    Jim

  • In reply to jim s:

    Jim,

      Sample rate is 6400 Mhz.LMFS(8118).SYSREF frequency is 1 Mhz ,K = 8 RBD =8.interpolation=1X.real mode..No error.DAC PLL is not used.NCO is not used.

    A0 8'h18
    A1 8'h30
    A2 8'h46
    A3 8'h59
    A4 8'h69
    A5 8'h75
    A6 8'h7C
    A7 8'h7E
    A8 8'h7C
    A9 8'h75
    A10 8'h69
    A11 8'h59
    A12 8'h46
    A13 8'h30
    A14 8'h18
    A15 8'h00
    A16 8'hE8
    A17 8'hD0
    A18 8'hBA
    A19 8'hA7
    A20 8'h97
    A21 8'h8B
    A22 8'h84
    A23 8'h82
    A24 8'h84
    A25 8'h8B
    A26 8'h97
    A27 8'hA7
    A28 8'hBA
    A29 8'hD0
    A30 8'hE8
    A31 8'h00

    This is my test data.

    Regards,

    Wuge

  • In reply to user4221793:

    Jim,

     

    • The picture is the result of my test

    Regards,test.docx

    Wuge

  • Guru 67320 points

    In reply to user4221793:

    Wuge,

    According to the JESD204B standard, the following equation must be satisfied;   17 F * K < 1023.

    Your K value is to low. Since F = 1, change K to 20. Give this a try. make sure to change this in the FPGA as well.


    Regards,

    Jim 

  • In reply to jim s:

    Jim ,

    Performance in DAC38RF82 81180 mode is encouraging.The value read in register 0x64 is 0x0002.On our board, we have two DAC38RF82. How to achieve synchronization?

    0x00 0x5860
    0x01 0x3080
    0x431 0x1000
    0x43B 0x1802
    0x43C 0x8229
    0x10A 0x8010
    0x10D 0x0000
    0x119 0x0001
    0x124 0x0030
    0x125 0x3000
    0x14A 0xFF03
    0x14B 0x1300
    0x14C 0x1307
    0x14D 0x0007
    0x14E 0x0707
    0x14F 0x1C60
    0x151 0x001F
    0x153 0x0000
    0x154 0x1CE7
    0x24A 0x0003
    0x124 0x0000
    0x15C 0x0000
    0x109 0x0004
    0x10A 0xFC03
    0x10A 0x7C03
    0x109 0x0000
    0x100 0x5863
    0x109 0x0001
    0x124 0x0020
    0x15C 0x0003
    0x109 0x0000
    0x100 0x5860
    0x109 0x0000
    0x104 0x0000
    0x105 0x0000

    This is my configuration, 20ms interval per write register.dac clk=6400Mhz,sysref=1Mhz .DAC PLL is not used.My problem is that I now need to write 0x0000 to 0x15C to get the output.I tried to write 0x0000 to 0x15C to get the output after the mode was configured, but the synchronization problem was not solved.

    Regards,

    Wuge

  • In reply to user4221793:

    Hi Wuge,

    To get the DACs properly synchronized you will have to use SYSREF. So writing 0x0 to 0x15C will cause them to not synchronize. Seeing that you have to write that to get an output may indicate that you are having a problem with the SYSREF. 

    One test to verify the DAC is capturing the SYSREF correctly is to test the output with the NCO. I attaching a power point that will guide you through the procedure.

    8546.SYSREF_NCO.pptx

    Regards,

    David Chaparro

  • In reply to David Chaparro:

    Hi David Chaparro,

            Since I don't have an EVM board right now.How do I get NCO only output?I wonder if there is something wrong with my SYSREF frequency.The value I read back from address 0x05 is 0x0139. Is that a problem?

    Regards,

  • In reply to user4221793:

    Hi,

    In order to perform the test mentioned above you will need theses register writes:

    •Add 0x10C  Data 0x2620
    •Add 0x127  Data 0x2828
    •Add 0x12F  Data 0x0001
    •Add 0x130  Data 0x0000
    •Add 0x11E  Data 0x8889
    •Add 0x11F  Data 0x8888
    •Add 0x120  Data 0x0888
    Regards,
    David Chaparro