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Hi Jim,
When I use DAC38RF82, I don't know how to frame the data.
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Regards,
Wuge
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Hi Jim,
When I use DAC38RF82, I don't know how to frame the data.
Regards,
Wuge
Wuge,
The Xilinx IP is a tad quirky when it comes to how data gets sorted, but if my understanding is correct, it will do the following:
The IP will have 8 lanes of 32 bits each (hence a total output of 256 bits)
I have illustrated the data packing in the attached document (for first 4 lanes only) for mode 81180. This applies for 8 total lanes.
In the next step, I have taken a 32 bit chunk and separated the data into four 8 bit packets. This is because the 8b/10b protocol works on 8bit granularity
As a final step, I have illustrated how the samples on Lane 0 will map to the rx_tdata[31:0] (from MSB to LSB)
The same mapping approach will apply to the other 7 lanes.
Regards,
Jim
Jim,
It has been confirmed that the group frames are ok.But I'm not sure if it's a configuration issue.When testing a single frequency signal, multiple tones are output.Attach information.
A0 8'h18 A1 8'h30 A2 8'h46 A3 8'h59 A4 8'h69 A5 8'h75 A6 8'h7C A7 8'h7E A8 8'h7C A9 8'h75 A10 8'h69 A11 8'h59 A12 8'h46 A13 8'h30 A14 8'h18 A15 8'h00 A16 8'hE8 A17 8'hD0 A18 8'hBA A19 8'hA7 A20 8'h97 A21 8'h8B A22 8'h84 A23 8'h82 A24 8'h84 A25 8'h8B A26 8'h97 A27 8'hA7 A28 8'hBA A29 8'hD0 A30 8'hE8 A31 8'h00
0x00 0x5860 0x01 0x3080 0x02 0xFFFF 0x03 0xFFFF 0x04 0x00FE 0x05 0x0007 0x40A 0x7C03 0x40B 0x0022 0x40C 0xA002 0x40D 0xF000 0x41B 0x0000 0x423 0xFFFF 0x424 0x1001 0x431 0x1000 0x432 0x0508 0x433 0x453C 0x434 0x0000 0x435 0x0018 0x43B 0x1802 0x43C 0x8229 0x43D 0x0088 0x43E 0x0909 0x43F 0x0000 0x10A 0x8050 0x10C 0x2402 0x10D 0x0000 0x10E 0x00FF 0x10F 0xFFFF 0x110 0xFFFF 0x111 0xFFFF 0x117 0x0000 0x119 0x0001 0x11C 0x0000 0x11D 0x0000 0x11E 0x0000 0x11F 0x0000 0x120 0x0000 0x121 0x0000 0x122 0x0000 0x123 0x0000 0x124 0x0030 0x125 0x3000 0x127 0x8888 0x128 0x0330 0x129 0x0000 0x12A 0x0000 0x12B 0x0000 0x12C 0x0000 0x12D 0x1FFF 0x12E 0x1FFF 0x12F 0x0000 0x130 0x0000 0x132 0x0400 0x133 0x0400 0x146 0x0044 0x147 0x190A 0x148 0x31C3 0x14A 0xFF03 0x14B 0x0700 0x14C 0x0707 0x14D 0x0007 0x14E 0x0F0F 0x14F 0x1CC1 0x150 0x0000 0x151 0x00FF 0x152 0x00FF 0x153 0x0000 0x154 0x0CE7 0x15C 0x0002 0x15E 0x0000 0x164 0x0000 0x165 0x0000 0x166 0x0000 0x167 0x0000 0x168 0x0000 0x169 0x0000 0x16A 0x0000 0x16B 0x0000 0x16C 0x0000 0x16D 0x0000 0x16E 0x0000 0x20A 0x8050 0x20C 0x2402 0x20D 0x0000 0x20E 0x00FF 0x20F 0xFFFF 0x210 0xFFFF 0x211 0xFFFF 0x217 0x0000 0x219 0x0001 0x21C 0x0000 0x21D 0x0000 0x21E 0x0000 0x21F 0x0000 0x220 0x0000 0x221 0x0000 0x222 0x0000 0x223 0x0000 0x224 0x0020 0x225 0x3000 0x227 0x8888 0x228 0x0330 0x229 0x0000 0x22A 0x0000 0x22B 0x0000 0x22C 0x0000 0x22D 0x1FFF 0x22E 0x1FFF 0x22F 0x0000 0x230 0x0000 0x232 0x0400 0x233 0x0400 0x246 0x0044 0x247 0x190A 0x248 0x31C3 0x24A 0x0003 0x24B 0x0700 0x24C 0x0700 0x24D 0x0007 0x24E 0x0F0F 0x24F 0x1CC1 0x250 0x0000 0x251 0x00FF 0x252 0x00FF 0x253 0x0000 0x254 0x0CE7 0x25C 0x0003 0x25E 0x0000 0x264 0x0000 0x265 0x0000 0x266 0x0000 0x267 0x0000 0x268 0x0000 0x269 0x0000 0x26A 0x0000 0x26B 0x0000 0x26C 0x0000 0x26D 0x0000 0x26E 0x0000 0x124 0x0000 0x15C 0x0000 0x109 0x0004 0x10A 0xFC03 0x10A 0x7C03 0x00 0x5863 0x124 0x0010 0x15C 0x0003 0x00 0x5860 0x04 0x0000 0x05 0x0000 0x164 0x0000 0x165 0x0000 0x166 0x0000 0x167 0x0000 0x168 0x0000 0x169 0x0000 0x16A 0x0000 0x16B 0x0000 0x16C 0x0000 0x16D 0x0000
Wuge,
What is the DAC clock sample rate? What is the LMFS setting? What SYSREF frequency are you using? What is the K and RBD values? What is the interpolation factor? Is the DAC using real data or I/Q data? One I/Q per channel or two? Are you using the DAC PLL? Are you reporting an errors? Are you using the NCO?
This info is in the config file you send but would take some time to get the info. Providing these answers will help me get back to you sooner.
Is the data file attached what you are sending to the DAC? Please also send a screen shot of the DAC output.
What is the group frame you are mentioning? Is the lane data sent from your FPGA?
Regards,
Jim
Jim,
Sample rate is 6400 Mhz.LMFS(8118).SYSREF frequency is 1 Mhz ,K = 8 RBD =8.interpolation=1X.real mode..No error.DAC PLL is not used.NCO is not used.
A0 8'h18
A1 8'h30
A2 8'h46
A3 8'h59
A4 8'h69
A5 8'h75
A6 8'h7C
A7 8'h7E
A8 8'h7C
A9 8'h75
A10 8'h69
A11 8'h59
A12 8'h46
A13 8'h30
A14 8'h18
A15 8'h00
A16 8'hE8
A17 8'hD0
A18 8'hBA
A19 8'hA7
A20 8'h97
A21 8'h8B
A22 8'h84
A23 8'h82
A24 8'h84
A25 8'h8B
A26 8'h97
A27 8'hA7
A28 8'hBA
A29 8'hD0
A30 8'hE8
A31 8'h00
This is my test data.
Regards,
Wuge
Wuge,
According to the JESD204B standard, the following equation must be satisfied; 17 < F * K < 1023.
Your K value is to low. Since F = 1, change K to 20. Give this a try. make sure to change this in the FPGA as well.
Regards,
Jim
Jim ,
Performance in DAC38RF82 81180 mode is encouraging.The value read in register 0x64 is 0x0002.On our board, we have two DAC38RF82. How to achieve synchronization?
0x00 0x5860
0x01 0x3080
0x431 0x1000
0x43B 0x1802
0x43C 0x8229
0x10A 0x8010
0x10D 0x0000
0x119 0x0001
0x124 0x0030
0x125 0x3000
0x14A 0xFF03
0x14B 0x1300
0x14C 0x1307
0x14D 0x0007
0x14E 0x0707
0x14F 0x1C60
0x151 0x001F
0x153 0x0000
0x154 0x1CE7
0x24A 0x0003
0x124 0x0000
0x15C 0x0000
0x109 0x0004
0x10A 0xFC03
0x10A 0x7C03
0x109 0x0000
0x100 0x5863
0x109 0x0001
0x124 0x0020
0x15C 0x0003
0x109 0x0000
0x100 0x5860
0x109 0x0000
0x104 0x0000
0x105 0x0000
This is my configuration, 20ms interval per write register.dac clk=6400Mhz,sysref=1Mhz .DAC PLL is not used.My problem is that I now need to write 0x0000 to 0x15C to get the output.I tried to write 0x0000 to 0x15C to get the output after the mode was configured, but the synchronization problem was not solved.
Regards,
Wuge
Hi Wuge,
To get the DACs properly synchronized you will have to use SYSREF. So writing 0x0 to 0x15C will cause them to not synchronize. Seeing that you have to write that to get an output may indicate that you are having a problem with the SYSREF.
One test to verify the DAC is capturing the SYSREF correctly is to test the output with the NCO. I attaching a power point that will guide you through the procedure.
Regards,
David Chaparro
Hi David Chaparro,
Since I don't have an EVM board right now.How do I get NCO only output?I wonder if there is something wrong with my SYSREF frequency.The value I read back from address 0x05 is 0x0139. Is that a problem?
Regards,
Hi,
In order to perform the test mentioned above you will need theses register writes:
Hi, David Chaparro
Tried with your method and failed to get output.My sampling clock is 6400MHZ.SYSREF is 1MHZ.The value of address 0x05 is 0x0139 what does that mean.
Hi Wuge,
I was looking at your register settings and noticed that you were writing 0x7C03 to address 0x10A. This changes the interpolation of DAC A to a value not supported in this mode. You have a different value written to it before, 0x8050, which works with this mode. Can you try the NCO test with the value of 0x8050 for register 0x10A.
Regards,
David
Hi,David
0x00 0x5860
0x01 0x3080
0x431 0x1000
0x43B 0x1802
0x43C 0x8229
0x10A 0x8010
0x10D 0x0000
0x119 0x0001
0x124 0x0030
0x125 0x3000
0x14A 0xFF03
0x14B 0x1300
0x14C 0x1307
0x14D 0x0007
0x14E 0x0707
0x14F 0x1C60
0x151 0x001F
0x153 0x0000
0x154 0x1CE7
0x24A 0x0003
0x124 0x0000
0x15C 0x0000
0x109 0x0004
0x40A 0xFC03
0x40A 0x7C03
0x109 0x0000
0x100 0x5863
0x109 0x0001
0x124 0x0020
0x15C 0x0003
0x109 0x0000
0x100 0x5860
0x109 0x0000
0x104 0x0000
0x105 0x0000
This is my configuration. Is there any problem?
Regards,
Wuge
Hi,David
Even if I configure it like this, there is still no output.I still need to write 0x00 to 0x5C to get the output.Is there a problem with my sysref, but I don't know where the adjustment can be improved.
Regards,
Wuge
Hi Wuge,
Can you share a capture of the output after you make that register write?
Thanks,
David