Part Number: DAC38RF82
When I use DAC38RF82, I don't know how to frame the data.
The Xilinx IP is a tad quirky when it comes to how data gets sorted, but if my understanding is correct, it will do the following:
The IP will have 8 lanes of 32 bits each (hence a total output of 256 bits)
I have illustrated the data packing in the attached document (for first 4 lanes only) for mode 81180. This applies for 8 total lanes.
In the next step, I have taken a 32 bit chunk and separated the data into four 8 bit packets. This is because the 8b/10b protocol works on 8bit granularity
As a final step, I have illustrated how the samples on Lane 0 will map to the rx_tdata[31:0] (from MSB to LSB)
The same mapping approach will apply to the other 7 lanes.
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In reply to jim s:
It has been confirmed that the group frames are ok.But I'm not sure if it's a configuration issue.When testing a single frequency signal, multiple tones are output.Attach information.test_data.txtDAC38RF8x.pdfconfig.txt
In reply to user4221793:
What is the DAC clock sample rate? What is the LMFS setting? What SYSREF frequency are you using? What is the K and RBD values? What is the interpolation factor? Is the DAC using real data or I/Q data? One I/Q per channel or two? Are you using the DAC PLL? Are you reporting an errors? Are you using the NCO?
This info is in the config file you send but would take some time to get the info. Providing these answers will help me get back to you sooner.
Is the data file attached what you are sending to the DAC? Please also send a screen shot of the DAC output.
What is the group frame you are mentioning? Is the lane data sent from your FPGA?
Sample rate is 6400 Mhz.LMFS(8118).SYSREF frequency is 1 Mhz ,K = 8 RBD =8.interpolation=1X.real mode..No error.DAC PLL is not used.NCO is not used.
A0 8'h18A1 8'h30A2 8'h46A3 8'h59A4 8'h69A5 8'h75A6 8'h7CA7 8'h7EA8 8'h7CA9 8'h75A10 8'h69A11 8'h59A12 8'h46A13 8'h30A14 8'h18A15 8'h00A16 8'hE8A17 8'hD0A18 8'hBAA19 8'hA7A20 8'h97A21 8'h8BA22 8'h84A23 8'h82A24 8'h84A25 8'h8BA26 8'h97A27 8'hA7A28 8'hBAA29 8'hD0A30 8'hE8A31 8'h00
This is my test data.
The picture is the result of my test
According to the JESD204B standard, the following equation must be satisfied; 17 < F * K < 1023.
Your K value is to low. Since F = 1, change K to 20. Give this a try. make sure to change this in the FPGA as well.
Performance in DAC38RF82 81180 mode is encouraging.The value read in register 0x64 is 0x0002.On our board, we have two DAC38RF82. How to achieve synchronization?
0x00 0x58600x01 0x30800x431 0x10000x43B 0x18020x43C 0x82290x10A 0x80100x10D 0x00000x119 0x00010x124 0x00300x125 0x30000x14A 0xFF030x14B 0x13000x14C 0x13070x14D 0x00070x14E 0x07070x14F 0x1C600x151 0x001F0x153 0x00000x154 0x1CE70x24A 0x00030x124 0x00000x15C 0x00000x109 0x00040x10A 0xFC030x10A 0x7C030x109 0x00000x100 0x58630x109 0x00010x124 0x00200x15C 0x00030x109 0x00000x100 0x58600x109 0x00000x104 0x00000x105 0x0000
This is my configuration, 20ms interval per write register.dac clk=6400Mhz,sysref=1Mhz .DAC PLL is not used.My problem is that I now need to write 0x0000 to 0x15C to get the output.I tried to write 0x0000 to 0x15C to get the output after the mode was configured, but the synchronization problem was not solved.
To get the DACs properly synchronized you will have to use SYSREF. So writing 0x0 to 0x15C will cause them to not synchronize. Seeing that you have to write that to get an output may indicate that you are having a problem with the SYSREF.
One test to verify the DAC is capturing the SYSREF correctly is to test the output with the NCO. I attaching a power point that will guide you through the procedure.
In reply to David Chaparro:
Hi David Chaparro,
Since I don't have an EVM board right now.How do I get NCO only output？I wonder if there is something wrong with my SYSREF frequency.The value I read back from address 0x05 is 0x0139. Is that a problem?
In order to perform the test mentioned above you will need theses register writes:
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