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AFE7799: Why does the number of SerDes pins need 8 pairs instead of 4 pairs?

Prodigy 40 points

Replies: 4

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Part Number: AFE7799

1.Why is the SerDes interface of the chip? 8 pairs of TX lanes and 8 pairs of Rx LANs, instead of 4 pairs of TX lanes and 4 pairs of Rx lanes. What are the benefits of adding so many pins?

2.What is the difference between afe7799 and afe7769? How should I choose one of them?

  • Hi,

    1. having more lanes can allow 1) reduction of serdes rate 2) aggregate of wider bandwidth. There are different JESD204 modes calls for 8 lanes for 4T4R2F

    2. it is the number of LOs for different use case. AFE7769 has 4 PLL, while AFE7799 has 1 PLL. You can request more information for detail on the TI webpage. Someone will review your business opportunity and approve the access.

    -Kang

  • In reply to Kang Hsia:

     2) aggregate of wider bandwidth. There are different JESD204 modes calls for 8 lanes for 4T4R2F

    ---------------------------------What does this mean? Is different jesd204 modes defined in the protocol?

    3.In addition, can you use 450MHz orx bandwidth to observe 200MHz transmit signal bandwidth? To achieve DPD function

  • In reply to user6468622:

    Hi,

    2) I meant that you do not need to use all 8 lanes at all time. If you bandwidth requirement is low or your serdes rate is high enough, two lanes or 4 lanes are enough

    3) yes, this is assuming your DPD requires only 450MHz to perform 200MHz IBW correction. 

    -kang

  • In reply to Kang Hsia:

    With regard to the SerDes configuration of jesd204, we hope to use 4 pairs of lanes to realize the DPD scheme of 600MHz observation bandwidth, and the lane rates of transmitter and receiver are the same.

    Is the following configuration OK?

    JESD204B, C Frame Format for TX Chain: L-M-F-S-Hd = 48410 (One Link)

    JESD204B, C Frame Format for RX Chain: L-M-F-S-Hd = 28810 (One Link)

    JESD204B, C Frame Format for FB Chain: L-M-F-S-Hd = 22210

    The second question is about "sysref input level" in Datasheet Page23:

    Is 350mVpp a differential signal level or a single ended signal level? Is this a bug? In my understanding, the single ended signal level of LVDS signal is 350mV, while the differential signal level of LVDS signal is 700mV.