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AFE7799: JESD204C Synchronization problem

Part Number: AFE7799
Other Parts Discussed in Thread: AFE7769EVM, AFE7769

Hi,

I am trying to communicate ZC102 EVM board with my AFE7769EVM-3p5 module via JESD204C. I am using Xilinx JESD204C  and JES204 PHY IPs. In Vivado I set Lane Rate to 8.11008 and refclk as 122.88Mhz. I am configuring AFE7769EVM board through Latte software. Main parameters of the python script is given below.

When I configure the FPGA and AFE7769 EVM using  I am observing invalid 2 bit sync headers , like 00,11, at the output of the JESD204PHY IP and synchronization cannot be established. (At the output of the transceivers) 

Apart from this EYE diagram of the lanes are close as expected (very bad) but I cannot see any reason for this because both cards are EVM should be correctly designed. 

Do you have any idea what the problem might be?  Do you have any example design for JESD204C  for ZCU 102 board. (You sent me an example design for JESD204B previously and  it is working.  So it seems that I need for JESD204C also :))

I think that my AFE configuration file might be incorrect. So do you have any Latte python configuration file for JESD204C?

Thanks in advance.

Tamer.

sysParams.FRef = 491.52
sysParams.Fs = 2949.12
sysParams.pllMuxModes = 0
#0: 4T4R Mode with PLL0 as Master. PLL 0 for all the LOs.
#1: 4T4R Mode with PLL2 as Master. PLL 2 for all the LOs.
#2: 4T4R FDD Mode. PLL0 for TX and PLL2 for RX.
#3: 2*2T2R FDD Mode: PLL0 AB-TX;PLL3 AB-RX; PLL2 CD TX; PLL4 CD RX
#4: 2T2R FDD - TDD Mode: PLL0 AB-TX; PLL3-AB-RX; PLL2 CD
sysParams.pllLo = [3500.01,sysParams.Fs,3501.06,1800.24,3400.0] #PLL Frequencies for PLLs [0,1,2,3,4]
sysParams.setTxLoFbNcoFreqForTxCalib = True

## In below parameters, first in the array is for first 2T2R1F and second 2T2R1F.

# JESD and Serdes Parameters
sysParams.useSpiSysref = False
sysParams.LMFSHdRx = ["28810","28810"]
sysParams.LMFSHdFb = ["12820","12820"]
sysParams.LMFSHdTx = ["48410","48410"]
sysParams.systemMode = [1,1] # 0-Identical, 1-FDD, 2-TDD
sysParams.dedicatedLaneMode = [1,1]
sysParams.jesdProtocol = 2#0#1#0 # -0:B; 1:H; 2:C
sysParams.serdesFirmware = True
sysParams.jesdTxLaneMux = [1,0,2,3,4,5,6,7]#[0,1,2,3,4,5,6,7] # RX1,RX2,RX3,RX4,FB1,FB2
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7]#[0,1,2,3,4,5,6,7]
sysParams.jesdRxRbd = [15, 15]
sysParams.jesdScr = [False,False]
sysParams.serdesTxLanePolarity = [False,False,False,False,True,True,True,True]
sysParams.serdesRxLanePolarity = [False,False,False,False,True,True,True,True]
sysParams.jesdK = [1,1]
sysParams.syncLoopBack = True
sysParams.jesdLoopbackEn = 1
sysParams.jesdTxRxABSyncMux = 0
sysParams.jesdTxRxCDSyncMux = 0
sysParams.jesdTxFBABSyncMux = 0
sysParams.jesdTxFBCDSyncMux = 0
sysParams.jesdRxABSyncMux = 0
sysParams.jesdRxCDSyncMux = 0
#sysParams.jesdABLvdsSync = True
#sysParams.jesdCDLvdsSync = True

# Decimation and interpolation Parameters
sysParams.ddcFactorRx = [24,24]
sysParams.ddcFactorFb = [12,12]
sysParams.ducFactorTx = [12,12]

sysParams.fbNco = [3500.01,3500.01]
sysParams.lowIfNcoRx = [0,0]
sysParams.lowIfNcoTx = [0,0]
sysParams.lowIfNcoFb = [0,0]

LMKParams.pllEn = True
LMKParams.lmkFrefClk = True
#LMKParams.inputClk = 1474.56
LMKParams.sysrefFreq = 3.84

if simulationMode==False:
setupParams.skipFpga=1
setupParams.skipLmk=0
AFE.skipRxConfig=0
AFE.skipFbConfig=0
AFE.skipTxConfig=0
AFE.skipAgc=0

sysParams.gpioConfigMode=1

'''
#PAP Config
sysParams.txDsaUpdateMode=1
for i in range(4):
sysParams.srConfigParams[i]['GainStepSize']=38
sysParams.srConfigParams[i]['AttnStepSize']=38
sysParams.srConfigParams[i]['AmplUpdateCycles']=6
sysParams.srConfigParams[i]['threshold']=30
sysParams.srConfigParams[i]['enable']=True
sysParams.srConfigParams[i]['mode']=10

#Ext AGC Config
for i in range(4):
sysParams.agcRegConfigParams[i]['enableIa']=0
sysParams.agcRegConfigParams[i]['phmOvrEn']=1
sysParams.agcRegConfigParams[i]['enableSa']=0
sysParams.agcRegConfigParams[i]['enableSd']=0
sysParams.agcRegConfigParams[i]['enableBa']=1
sysParams.agcRegConfigParams[i]['gainControl']=4
sysParams.agcRegConfigParams[i]['fdsaOffset']=6

#INT Pins
sysParams.intPinsParams[0]['JESD']=True
sysParams.intPinsParams[0]['SPI']=True
sysParams.intPinsParams[0]['SRTXA']=True
sysParams.intPinsParams[0]['SRTXB']=True
sysParams.intPinsParams[0]['SRTXC']=True
sysParams.intPinsParams[0]['SRTXD']=True
sysParams.intPinsParams[0]['PLL0']=True
sysParams.intPinsParams[0]['PLL1']=True
sysParams.intPinsParams[0]['PLL2']=True
sysParams.intPinsParams[0]['PLL3']=True
sysParams.intPinsParams[0]['PLL4']=True
'''

#Calibrations
sysParams.enableRxDsaFactoryCal = False
sysParams.enableTxDsaFactoryCal = False
sysParams.enableTxIqmcLolTrackingCorr = False
sysParams.enableRxIqmcLolTrackingCorr = True
sysParams.txIqMcCalibMode = 0 # 0 -Single Fb Mode FB AB ; 1 -Single Fb Mode FB CD ; 2- Dual Fb_Mode
sysParams.txDsaCalibMode = 0
sysParams.rxDsaCalibMode = 0

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\config.txt")
logDumpInst.logFormat=0x4
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1

device.optimizeWrites=0
device.rawWriteLogEn=1
device.rewriteFile=1
device.rawWriteLogsFile=ASTERIX_DIR+DEVICES_DIR+r"\test.txt"#"D:\AFE77xx_config/testBroadcast.txt"
lmk.rawWriteLogEn=0
lmk.rawWriteLogsFile=device.rawWriteLogsFile

# AFE.initializeConfig()
AFE.deviceBringup()

device.rawWriteLogEn=1
lmk.rawWriteLogEn=0

engine.sampleNo=32768

AFE.TOP.overrideTdd(1, 1, 1)

  • Hello Tamer,

    Thank you for your update

    Regarding your question:

    tamer gudu said:
    When I configure the FPGA and AFE7769 EVM using  I am observing invalid 2 bit sync headers , like 00,11, at the output of the JESD204PHY IP and synchronization cannot be established. (At the output of the transceivers) 

    I am assuming you are talking about the AFE7769 EVM uplink (from RF receiver to JESD204 TX of the AFE, to the JESD204 RX of your FPGA). Is this correct?

    Could you please provide the Vivado capture of the sync header error? A snapshot of a multi-block (i.e 32x of blocks) should be sufficient.

    The AFE7769 only supports CRC3 and CRC12. It does not support FEC. Could you please double check if the Xilinx JESD204C IP is configured the same way?

    If it is the AFE7769 downlink (of the RF transmitter of JESD204 RX of the AFE, from the data stream of the JESD204 TX of the FPGA), then we will have to see if the Xilinx IP is properly configured. If the AFE7769 detected sync header error, you will see error being generated when performance AFE.adcDacSync() command.

    Another thing to double check is whether the FPGA and AFE EVM have a common reference source. The 122.88MHz clock is generated from the ZCU102 EVM or the AFE7769 EVM? The 122.88MHz clock should come from the AFE7769 EVM so both the FPGA and AFE EVM share the same common clock source to avoid drift of the data. 

    Regarding your next question:

    tamer gudu said:
    Apart from this EYE diagram of the lanes are close as expected (very bad) but I cannot see any reason for this because both cards are EVM should be correctly designed. 

    Which side of the capture are you referring to? Is this also the FPGA side? We have capabilities to perform eye diagrams on the AFE7769 side. I believe we have shared the commands with you already. 

    One of the colleague, Satish, will be back from vacation after the New Year. We will check your setup with our TSW14J58 EVM once we return and see if we have the same issue. The current TSW14J58 EVM is using Xilinx JESD204C IP. 

    Our TI's own JESD204C may take a bit more time to get to the 64b/66b encoding. I will inquire the team also after the New Year. Thanks a lot.

    -Kang

  • Hi,

    Thanks for quick reply.

    I am assuming you are talking about the AFE7769 EVM uplink (from RF receiver to JESD204 TX of the AFE, to the JESD204 RX of your FPGA). Is this correct?

    Yes. I am talking about AFE to FPGA.

    Could you please provide the Vivado capture of the sync header error?

    Here is the capture of sycn header error. I took the capture from the PHY output. As you may know Xilinx JESD204C IP composed of two part. One includes the transceivers (JESD204 PHY) and other for JESD protocol. The data is taken from the output of the PHY.  At the output of the PHY I am expecting that SYNC signal should be high because I am assuming that it shows me a correct sync headers are found. I verify this assumption with simulation. In the simulation it goes high after a while.

    The AFE7769 only supports CRC3 and CRC12. It does not support FEC. 

    In Xilinx JESD IPs this check is made in JESD204C section (there is a configuration option) not in JESD204C PHY part. My problem is exist before FEC control.

    Another thing to double check is whether the FPGA and AFE EVM have a common reference source. The 122.88MHz clock is generated from the ZCU102 EVM or the AFE7769 EVM? 

    I connect refclk  of JESD_PHY IP  to the LMK output of GTXCLK (122.88) though FMC connector. The core clock is obtained from this clock also using BUF_GTs as explanied in the user manual of JESD IP. I also connect refclk of AFE EVM to refclk of Xilinx IP. So the answer is yes, they have a common reference source. I am assuming routing of the clocks are good because both cards are EVM.

     Which side of the capture are you referring to? Is this also the FPGA side?  

    Yes. I capture bus at the output of the JESD204 PHY (output of GT transceivers). 

    Also I should correct that my Xilinx EVM board is ZCU111 not ZCU102 which is wrongly written in the previous post but I dont think that it is a matter because both use Zynq MPSOC.

     We will check your setup with our TSW14J58 EVM once we return and see if we have the same issue. 

    Here is the complete Python file that I am use to obtain the capture given above.

    Thanks for your help.

    Happy new year.

    Tamer.

    2T2R FDD Mode: PLL0 AB-TX;PLL3 AB-RX; PLL2 CD TX; PLL4 CD RX
    #4: 2T2R FDD - TDD Mode: PLL0 AB-TX; PLL3-AB-RX; PLL2 CD
    sysParams.pllLo = [3500.01,sysParams.Fs,3501.06,1800.24,3400.0] #PLL Frequencies for PLLs [0,1,2,3,4]
    sysParams.setTxLoFbNcoFreqForTxCalib = True

    ## In below parameters, first in the array is for first 2T2R1F and second 2T2R1F.
    # JESD and Serdes Parameters
    sysParams.useSpiSysref = False
    sysParams.LMFSHdRx = ["28810","28810"]
    sysParams.LMFSHdFb = ["12820","12820"]
    sysParams.LMFSHdTx = ["48410","48410"]
    sysParams.systemMode = [1,1] # 0-Identical, 1-FDD, 2-TDD
    sysParams.dedicatedLaneMode = [1,1]
    sysParams.jesdProtocol = 2#0#1#0 # -0:B; 1:H; 2:C
    sysParams.serdesFirmware = True
    sysParams.jesdTxLaneMux = [1,0,2,3,4,5,6,7]#[0,1,2,3,4,5,6,7] # RX1,RX2,RX3,RX4,FB1,FB2
    sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7]#[0,1,2,3,4,5,6,7]
    sysParams.jesdRxRbd = [15, 15]
    sysParams.jesdScr = [False,False]
    sysParams.serdesTxLanePolarity = [False,False,False,False,True,True,True,True]
    sysParams.serdesRxLanePolarity = [False,False,False,False,True,True,True,True]
    sysParams.jesdK = [1,1]
    sysParams.syncLoopBack = True
    sysParams.jesdLoopbackEn = 1
    sysParams.jesdTxRxABSyncMux = 0
    sysParams.jesdTxRxCDSyncMux = 0
    sysParams.jesdTxFBABSyncMux = 0
    sysParams.jesdTxFBCDSyncMux = 0
    sysParams.jesdRxABSyncMux = 0
    sysParams.jesdRxCDSyncMux = 0
    #sysParams.jesdABLvdsSync = True
    #sysParams.jesdCDLvdsSync = True

    # Decimation and interpolation Parameters
    sysParams.ddcFactorRx = [24,24]
    sysParams.ddcFactorFb = [12,12]
    sysParams.ducFactorTx = [12,12]

    sysParams.fbNco = [3500.01,3500.01]
    sysParams.lowIfNcoRx = [0,0]
    sysParams.lowIfNcoTx = [0,0]
    sysParams.lowIfNcoFb = [0,0]

    LMKParams.pllEn = True
    LMKParams.lmkFrefClk = True
    #LMKParams.inputClk = 1474.56
    LMKParams.sysrefFreq = 3.84

    if simulationMode==False:
    setupParams.skipFpga=1
    setupParams.skipLmk=0
    AFE.skipRxConfig=0
    AFE.skipFbConfig=0
    AFE.skipTxConfig=0
    AFE.skipAgc=0

    sysParams.gpioConfigMode=1

    '''
    #PAP Config
    sysParams.txDsaUpdateMode=1
    for i in range(4):
    sysParams.srConfigParams[i]['GainStepSize']=38
    sysParams.srConfigParams[i]['AttnStepSize']=38
    sysParams.srConfigParams[i]['AmplUpdateCycles']=6
    sysParams.srConfigParams[i]['threshold']=30
    sysParams.srConfigParams[i]['enable']=True
    sysParams.srConfigParams[i]['mode']=10

    #Ext AGC Config
    for i in range(4):
    sysParams.agcRegConfigParams[i]['enableIa']=0
    sysParams.agcRegConfigParams[i]['phmOvrEn']=1
    sysParams.agcRegConfigParams[i]['enableSa']=0
    sysParams.agcRegConfigParams[i]['enableSd']=0
    sysParams.agcRegConfigParams[i]['enableBa']=1
    sysParams.agcRegConfigParams[i]['gainControl']=4
    sysParams.agcRegConfigParams[i]['fdsaOffset']=6

    #INT Pins
    sysParams.intPinsParams[0]['JESD']=True
    sysParams.intPinsParams[0]['SPI']=True
    sysParams.intPinsParams[0]['SRTXA']=True
    sysParams.intPinsParams[0]['SRTXB']=True
    sysParams.intPinsParams[0]['SRTXC']=True
    sysParams.intPinsParams[0]['SRTXD']=True
    sysParams.intPinsParams[0]['PLL0']=True
    sysParams.intPinsParams[0]['PLL1']=True
    sysParams.intPinsParams[0]['PLL2']=True
    sysParams.intPinsParams[0]['PLL3']=True
    sysParams.intPinsParams[0]['PLL4']=True
    '''

    #Calibrations
    sysParams.enableRxDsaFactoryCal = False
    sysParams.enableTxDsaFactoryCal = False
    sysParams.enableTxIqmcLolTrackingCorr = False
    sysParams.enableRxIqmcLolTrackingCorr = True
    sysParams.txIqMcCalibMode = 0 # 0 -Single Fb Mode FB AB ; 1 -Single Fb Mode FB CD ; 2- Dual Fb_Mode
    sysParams.txDsaCalibMode = 0
    sysParams.rxDsaCalibMode = 0

    logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\config.txt")
    logDumpInst.logFormat=0x4
    logDumpInst.rewriteFile=1
    logDumpInst.rewriteFileFormat4=1

    device.optimizeWrites=0
    device.rawWriteLogEn=1
    device.rewriteFile=1
    device.rawWriteLogsFile=ASTERIX_DIR+DEVICES_DIR+r"\test.txt"#"D:\AFE77xx_config/testBroadcast.txt"
    lmk.rawWriteLogEn=0
    lmk.rawWriteLogsFile=device.rawWriteLogsFile

    # AFE.initializeConfig()
    AFE.deviceBringup()

    device.rawWriteLogEn=1
    lmk.rawWriteLogEn=0

    engine.sampleNo=32768

    AFE.TOP.overrideTdd(1, 1, 1)

     

     

  • Do you have any idea about the problem?

  • Hi Kang,

    I sent the Vivado capture pics. Do you have any idea about the problem :)

    Thanks.

    Tamer.

  • Hi Tamer,

    There seems to be some issues in 64/66b mode with the existing version of Latte. Please download and install the latest v2.18 Latte and recheck. We have checked a few JESD204C 64/66b mode encoding and seems to work well

    https://txn.box.com/s/suilorzar9pgzwuptvkuzgxtt245cvdk

    -Kang

  • Hi Kang,

    I installed new revision of Latte and config AFE with the file generated by this version. At last I started to see the 

    correct sync headers and sync signal. Great!. Thank you very much for your help. I have two more questions:

    1. I have downloaded AFE Technical Reference Manual from TI Secure Sofware. The revision date of the document is November 2019. Is there a new version of the 

        document?

    2. When I try to configure AFE with a line rate of  8.11008 Gbps , Latte configure LMK clock output that goes to FPGA GT reference clock input as 1/33th of the line rate, 245.76.

        Should it be 1/66th of the line rate which is 122.88MHz ? Are there any intention?  Because Xilinx FPGA JESD IP requires core clock rate as 1/66th of the line rate.

    Have a nice day,

    Dr. Tamer Güdü

  • Hi Dr. Tamer Güdü

    tamer gudu said:

    1. I have downloaded AFE Technical Reference Manual from TI Secure Sofware. The revision date of the document is November 2019. Is there a new version of the 

        document?

    Yes, this is the latest version of the TRM.

    tamer gudu said:

    2. When I try to configure AFE with a line rate of  8.11008 Gbps , Latte configure LMK clock output that goes to FPGA GT reference clock input as 1/33th of the line rate, 245.76.

        Should it be 1/66th of the line rate which is 122.88MHz ? Are there any intention?  Because Xilinx FPGA JESD IP requires core clock rate as 1/66th of the line rate.

    The original intention is to configure the FPGA clocks needed by our TSW14J56 EVM. You can always change the reference clock to the FPGA based on your needs through the following command line. Please add this in your configuration script and then execute the script to complete the setup. Below line configures the FPGA clock to 184.32MHz, for example.

    setupParams.fpgaRefClk = 184.32