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AFE7444EVM: Questions of using AFE7444EVM with Xillinx KCU105

Ryan Lee TW
Intellectual 506 points
Part Number: AFE7444EVM
Other Parts Discussed in Thread: AFE7444

Hi guys,

I am running AFE7444 EVM with Xilinx KCU105 .

Xilinx JESD204 IP Parameter Setting:

Constraints

Configuration Page.

Share Logic Page.

Default Link Parameters Page.

JESD204 PHY Configuration Page.

ILA Debug diagram

AFE7444EVM Parameter Setting:

We’re using Mode#6, Rx LMFS at 44210.

AFE74xx GUI Setting.

KCU105 detected refclk from AFE7444EVM is about 185MHz in selected Mode#6

Rx_JESD Register Request (FPGA side)

JESD Reg addr < 0x38 > : JESD_Rx SYNC status

JESD Reg addr < 0x3C > : JESD_Rx Debug Status

 

 

Recive Serdes Lane data:

JESD rx_tdata[255:0]

AFE7444 A_IN1 ( J14 ) without RF in

Vivado ILA

AFE7444  A_IN1 ( J14 ) with 3GHz RF single tone signal input.And Set AFE7444 Rx NCO 2990.

Xilinx ILA

Here are the 2 questions I've got as below:

  1.  Rx sample rate is 3GHz, TI Mode#6 decimation is x8, so the data bandwidth is 3000/8 = 375MHz, and using *.cfg file which is TI provided. And read the register from AFE7444, is the refclk = 185 MHz right?
  2.  How to separate the resolution of 256-bits rx_data to 4 channel (A, B, C, D) IQ data? (Both the scrambler of AFE7444 and KCU105 are confirmed to be closed)
  • 0
    TI__Genius 10505 points

    Hi Ryan,

    You mentioned that Rx NCO is set to 2990MHz. Please note that RF frequency band close to Rx sampling rate can not be used due to aliasing. You have to chose a different sampling rate (like 2.25GSPS for example).

    Please find my responses to your questions below:

    1. Rx sample rate is 3GHz, TI Mode#6 decimation is x8, so the data bandwidth is 3000/8 = 375MHz, and using *.cfg file which is TI provided. And read the register from AFE7444, is the refclk = 185 MHz right?

    Vijay: It looks like you are using on-board clock. So Rx sampling rate is 2949.12 MSPS. Output Data Rate is 2949.12 / 8 = 368.64 MSPS per each complex output channel (I and Q output). Usable bandwidth is about 80% of data rate (~300MHz). Using config file generated using TI GUI, ref clock = 184.32 MHz.

    2. How to separate the resolution of 256-bits rx_data to 4 channel (A, B, C, D) IQ data? (Both the scrambler of AFE7444 and KCU105 are confirmed to be closed)

    Vijay: A KCU105 FPGA reference design is available for this JESD mode on AFE7444 secure folder (at ti.com/mysecuresoftware). Please refer to that for these details. 

    Regards,

    Vijay