Other Parts Discussed in Thread: AFE7769
Hi team,
I have a quesiton about JESD204C transport layer of AFE7769 in TX direction (from FPGA to DAC).
I am using TX side of AFE7769 transceiver in JESD204C 48410 mode. For this purpose I am using the configuration file that is generated by Latte tool. To send data to transceiver I am using Zcu102 board and Xilinx JESD204C IP.
Observation 1:
With this configuration when I give 256 bit AXI stream data to Xilinx JESd204C IP as:(255 downto 0)
4x{sample2_sine[7:0], sample2_sine[15:8], sample2_cos[7:0], sample2_cos[15:8], sample1_sine[7:0], sample1_sine[15:8], sample1_cos[7:0], sample1_cos[15:8]}
(this order is the same order as given in transport_layer_afe77xx_48410.v file in AFE7769 example design for ZCU102 board that you send me previously.)
I cannot observe single tone at the output of the transceiver.
Observation 2:
But when I changed the order of bytes as (255 downto 0):
4x{sample2_sine[15:8], sample2_sine[7:0], sample2_cos[15:8], sample2_cos[7:0], sample1_sine[15:8], sample1_sine[7:0], sample1_cos[15:8], sample1_cos[7:0]}
I get the single to pulse at the output of the transceiver but this time the noise floor was very high (40 db below peak, with 16 bit DDS).
As you know the example design is for JESD204B links. Is there an order difference in transport layer of JESD204B and JESD204C configuration? (I am expecting that transport layer of JESD204C and B of the AFE7769 should be same. )
If there is a difference, what is the correct order?
Have nice day,
Dr. Tamer Güdü