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AFE7769-3P5EVM: Questions

Part Number: AFE7769-3P5EVM
Other Parts Discussed in Thread: AFE7769EVM, AFE7769

Hi Expert,

Customer is evaluating AFE7769EVM + TSW14J56EVM. When they tried to send out 100Mhz CW tone, they can see it at HSDC_Pro but didn’t see it at output of AFE7769EVM. The Latte GUI showing error message “automatic reset of FPGA will not be supported” Do you have any idea what does that mean and how to fix it?

 

Thanks,

Allan

  • Hi Allan,

    I believe the automatic reset of the FPGA error code is due to the fact we are using TSW14J56 EVM. There is no reset connection between the TSW14J56 EVM and the AFE7769 EVM. Therefore it is just a caution saying the Latte cannot reset the TSW14J56 EVM is the reset FPGA command is issued. This is within expectation.

    However, I believe you have run into issue when executing the actual Python script. Could you please advise the script that you have executed? This way Satish can comment on this better once he get to this thread.

    Thanks

    -Kang

  • Hi Allan,

    You can ignore that warning (“automatic reset of FPGA will not be supported”). After you send the DAC pattern from HSDC pro, can you run AFE.adcDacSync(1) in Latte's command line?

    Also, the bring-up script you run to configure AFE should match the parameters in the INI file you use for DAC. These are JESD parameters in addition to lanes used etc. Have you verified if those match? In other words, have you been able to send a CW from HSDC Pro and get it out of AFE's TX? I'm checking if the problem is with getting the DAC synced in general or if it is something to do with this 100Mhz file in particular.

    regards,

    satish.