DAC38RF80: Output power gain is Non-Linearity

Guru 17695 points
Part Number: DAC38RF80

Attached test results for Input to Output Gain look like non-linearity.

Please let me know about the reason of non-linearity.

I assumed that output gain is constant, because not using input Gain adjustment.

But below test results are change the output gain.

I want to know these results depend on DAC38RF80 spec or external problem.

※Orange: 10dB, Blue: 5dB, Light blue: 0dB, Green: -5dB

Please see test condition below;

・Signal generator (SG) output CW: 3.96GHz

・DAC38RF80 receive signal from FPGA, and confirmed DAC output signal on spectrum analyzer (SA).

・On above condition, DAC output gain measured on the condition of input level and DAC GAIN changing.

 (DAC GAIN are set 10dB, 5dB, 0dB, and -5dB)

Best regards,


  • Hello,

    There was a separate thread to our direct email. We have inquired the following:

    Please provide guidance on the ADC being used. You mentioned that output power level looks non-linear and depends on the input level. Where is the input level being referred?


    Is it from the SG -> RF circuit -> ADC -> FPGA -> DAC?

    Or is it only FPGA -> DAC (without data from ADC).


    Please advise. Eben can then take a look at this problem.

  • Hi Kang

    Thank you for reply,

    I looking forward answer by Eben or Kang.

    Input revel is referred on  SG -> RF circuit area.

    When SG -> RF circuit area set -20dBm level, FPGA's digital area become -35dBFS.  

    Please let me know if you need additional information or condition.

    Best regards,


  • Hi Satoshi,

    Please ask the customer to decouple the ADC in the linearity testing. Please ask the customer to send out signal only from the FPGA to the DAC. Check the performance again when FPGA send signal (i.e. single tone, two tone, etc) and match the datasheet condition. This step is needed to ensure the DAC is compliant to the datasheet performance. Right now you are getting combinations of SG, RF circuits, ADCs and other signal chain linearity performance. 

  • Hi Kang

    I apologize my reply delay,

    FPGA single tone was not have, instead of customer information below,

    ・I update gain graph for RF to DAC output below. (Vertical axis is gain: dB, horizontal axis is input level: dBm)

    ・Next, below is the relation for RF to DAC input side (= FPGA output side), RF input is changing and DAC gain is fixed -5dB.

     I looked like linearly specification.

      (Vertical axis is DAC input gain: dBFS, horizontal axis is input level: dBm)

    ・Below is customer measured "DAC input revel" - "RF input level".

     It looked like these level is flat and guess the non-linearity is any affect from DAC output side. 

      (Vertical axis is DAC input - RF input: dB, horizontal axis is input level: dBm)

    Please let me know if there any advice or need additional information.

    Best regards,


  • Satoshi-san,

    Regarding your feedback from the customer:

    FPGA single tone was not have,

    Based on what I am seeing, the customer reports that the gain is varying on the DAC side. However, all the data has the overall RF input to the DAC. If there are gain variations in the RF chain, the DAC will be impacted. Please emphasize the importance of sending FPGA single tone, and check the DAC output itself.

    The FPGA single tone should have varying power level, and check the DAC output. The gain of the DAC should stay flat.

    I.e. Pin vs. Pout should be a linear line with slope of 1dB/1dB. 

    i.e. Gain vs. Pin should be flat line with a constant gain.

    I update gain graph for RF to DAC output below. (Vertical axis is gain: dB, horizontal axis is input level: dBm)

    Please advise the difference of four lines. Which line is the expected line? if the vertical axis is gain (dB), we should expect flat line, correct? What are the different settings in these four lines that causes the gain to change? 

    Please double check if the vertical axis is indeed gain, as oppose to Pout.

    What does the customer mean by "DAC gain", please advise. Which adjustment is made within the DAC to have these four lines generated? 

  • Hi Kang

    Thank you for advice.

    I requesting to customer about get FPGA single tone.

    About RF to DC output graph, I apologize less information.

     ・Yellow: +5dB, Gray: 0dB, Orange: -5dB, Blue: -10dB

    ・Vertical axis is gain (dB).

    ・"DAC gain" is setting gain of four above lines.

    ・Yes, customer's expect is flat line, and prove the reason of non-flat line.

    Best regards,