RF & microwave forum - Recent Threads

AFE7950-SP: AFE7950-SP S-parameter/IBIS/DAC/ADC Simulation Files

Nathan Schram — Mon, 18 May 2026 19:12:01 GMT

Part Number: AFE7950-SP

Hello,

I'm looking for reference files to simulate the ADC/DAC side of the AFE7950-SP in AWR/ADS front-end simulations. Can you please provide the measured responses of the chipset and/or die along with IBIS files for the digital interfaces.

Thanks,

Nathan

AFE7950: AFE7950 Incomplete configuration options in Latte

Andrew Martin — Mon, 18 May 2026 15:37:25 GMT

Part Number: AFE7950

Hi,

I have been looking to bring up the AFE7950 with either the Latte tool or the provided register map for a new design we are working on - however I am having some difficulty with both methods.

The version of Latte (tool 2.9, framework 5.7.3) provided seems to be missing quite a few features compared to the documentation provided with it; notably I am missing the GPIO-MuxSel and PAP tabs. I cannot seem to genereate a SPI log either.

Does the Latte tool only work with the EVM boards? Is it possible to generate a configuration without?

I looked at using the register map in the TRM (SBAU337); however it seems to be a draft version from May 2020 (it has DRAFT in large bold letters watermarking every page) - and is missing infomation on some features mentioned in the datasheet.

Would it be possible for you to provide us with the non draft version of SBAU337 or access to older versions of the Latte tool?

Kind regards,
Andrew

AFE7950EVM: Issue of unknown signal on specific NCOs without input and modulated signal on some other NCOs with RF input

Noumeer Piracha — Mon, 18 May 2026 12:56:32 GMT

Part Number: AFE7950EVM

We're using the AFE7950EVM together with a 19EG Dev Board. Our goal is to use the AFE as a receiver and capture three channels of data for my application. For this, I made two different iterations of the project — one with 245.76 MHz BW and another with 983.04 MHz BW.

Project settings:

983.04 MHz BW:

The 983.04 MHz BW project has the following settings:

system mode = 3

JESD protocol = C

fpgaRefClk = 245.76 MHz

FRef = 491.52 MHz

LMFSHdRx = 44210

FadcRx = 2.94912 GHz

ddcFactorRx = 3

sysrefFreq = 7.68 MHz

Lane rate = 16.22016 G

245.76 MHz BW:

The 245.76 MHz BW project has the following settings:

system mode = 0

JESD protocol = B

fpgaRefClk = 245.76 MHz

FRef = 491.52 MHz

LMFSHdRx = 12410

FadcRx = 2.94912 GHz

ddcFactorRx = 12

sysrefFreq = 7.68 MHz

Lane rate = 9.8304 G

Issues:

Testing of the 983.04 MHz BW version went smoothly at 5 GHz and 9.425 GHz NCO. But during testing at different NCOs, two issues were identified.

Issue 1:

I observed that while the input is terminated a signal is being appeared at specific NCO, but after analysis this same behavior was being observed across a whole range of NCOs, in both projects.

983.04 MHz BW:

The sweep results for different NCO summarized below:

5 GHz to 5.36 GHz — correct.
5.37 GHz to 6.44 GHz — incorrect.
6.45 GHz to 8.31 GHz — correct.
8.32 GHz to 9.39 GHz — incorrect.
9.4 GHz to 11.26 GHz — correct.
Greater than 11.27 GHz — incorrect.

So there is roughly a 1.07 GHz range in which any selected NCO produces a system-induced signal.

For the 983.04 MHz configuration, I am reconstructing 4×32-bit IQ samples from two 64-bit JESD lanes that carry I and Q separately. The data shown below is a single 32-bit sample (one out of four per clock), included for debugging purposes.

5 GHz NCO with input terminated

5 GHz NCO FFT

6 GHz NCO with input terminated

6 GHz NCO FFT

8.8 GHz NCO with input terminated

8.8 GHz NCO FFT

245.76 MHz BW:

To check whether this behavior was specific to 983.04, I then tested the previously built 245.76 MHz BW version, which had been running at 5 GHz NCO the whole time. I observed a similar situation, but at a different NCO and over a shorter range.

Again, during the sweep, with the input terminated the AFE was showing a signal. The sweep observations are as follows:

5 GHz to 5.76 GHz — correct.
5.77 GHz to 6.03 GHz — incorrect.
6.04 GHz to 8.710 GHz — correct.
8.710 GHz to 8.980 GHz — incorrect.

So here it is roughly a 260 to 270 MHz range in which any selected NCO produces a system-induced signal.

5 GHz NCO with input terminated

5 GHz NCO signal FFT

6 GHz NCO with input terminated

6 GHz NCO signal FFT

8.8 GHz NCO with input terminated

8.8 GHz NCO signal FFT

Why this issue is occurring, is there any issue with configuration or any other possible solution to it?

Issue 2:

From above the 7.1 GHz to 7.86 GHz range, falls under correct behavior, but when I try to give an input signal at this frequency in 983.04 MHz BW project, the input seems like a modulated sinewave. Even from the FFT analysis it can seen another frequency component in present in the signal. The below input signal is at 7.505 GHz RF with NCO at 7.5 GHz. This issue was not observed in 245.76MHz.

Issue in the 7.1 to 7.86 GHz range

FFT

Latte 983.04 MHz BW:

setupParams.skipFpga = 1

sysParams = AFE.systemParams

setupParams.fpgaRefClk = 245.76

AFE.systemStatus.loadTrims = 1

sysParams.FRef = 491.52

sysParams.FadcRx = 2949.12

sysParams.FadcFb = 2949.12

sysParams.Fdac = 2949.12 * 4

sysParams.rxEnable = [True,True,True,True]

sysParams.txEnable = [False,False,False,False]

sysParams.fbEnable = [False,False]

sysParams.enableDacInterleavedMode = False

sysParams.modeTdd = 0

sysParams.topLevelSystemMode = 'StaticTDDMode'

sysParams.RRFMode = 5

sysParams.jesdSystemMode = [3,3]

sysParams.jesdLoopbackEn = 0

sysParams.LMFSHdRx =['44210', '44210', '44210', '44210']

sysParams.LMFSHdFb = ["22210","22210"]

sysParams.LMFSHdTx = ["44210","44210","44210","44210"]

sysParams.jesdTxProtocol = [2,2]

sysParams.jesdRxProtocol = [2,2]

sysParams.serdesFirmware = True

sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7]

sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7]

sysParams.jesdRxRbd = [4, 4]

sysParams.jesdTxRbd = [1, 1]

sysParams.rxJesdTxScr = [False,False,False,False]

sysParams.fbJesdTxScr = [False,False]

sysParams.jesdRxScr = [False,False,False,False]

sysParams.rxJesdTxK = [1,1,1,1]

sysParams.fbJesdTxK = [1,1]

sysParams.jesdRxK = [1,1,1,1]

sysParams.ncoFreqMode = "FCW"

sysParams.txNco0 = [[7500,7500],[7500,7500],[7500,7500], [7500,7500]]

sysParams.rxNco0 = [[7500,7500], [7500,7500], [7500,7500], [7500,7500]]

sysParams.fbNco0 = [2600,2600] #FBA, FBC for NCO0

sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual

sysParams.numBandsFb = [0,0]

sysParams.numBandsTx = [0,0,0,0]

sysParams.ducFactorTx = [12,12,12,12]

sysParams.ddcFactorFb = [3,3]

sysParams.ddcFactorRx = [3,3,3,3]

lmkParams.pllEn = True #False

lmkParams.inputClk = 1474.56 #737.28

lmkParams.sysrefFreq = 7.68

lmkParams.lmkFrefClk = True

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")

logDumpInst.logFormat = 0x00

logDumpInst.rewriteFile = 1

logDumpInst.rewriteFileFormat4 = 1

device.optimizeWrites = 0

device.rawWriteLogEn = 1

sysParams.jesdABLvdsSync = 0

sysParams.jesdCDLvdsSync = 0

sysParams.rxJesdTxSyncMux = [0,0,0,0]

sysParams.fbJesdTxSyncMux = [0,0]

sysParams.jesdRxSyncMux = [0,0,0,0]

sysParams.syncLoopBack = True

sysParams.gpioMapping={

'H8': 'ADC_SYNC0',

'H7': 'DAC_SYNC0',

'N8': 'ADC_SYNC2',

'N7': 'ADC_SYNC3',

'H9': 'ADC_SYNC1',

'G9': 'DAC_SYNC1',

'N9': 'DAC_SYNC2',

'P9': 'DAC_SYNC3',

'P14': 'GLOBAL_PDN',

'K14': 'FBABTDD',

'R6': 'FBCDTDD',

'N13': ['TXATDD','TXBTDD'],

'V5': ['TXCTDD','TXDTDD'],

'H12': ['RXATDD','RXBTDD'],

'R15': ['RXCTDD','RXDTDD']}

setupParams.skipLmk = False

AFE.initializeConfig()

lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq

lmkParams.lmkPulseSysrefMode = False

AFE.LMK.lmkConfig()

setupParams.skipLmk = True

AFE.deviceBringup()

AFE.TOP.overrideTdd(15,0,15)

Latte 245.76 MHz BW:

setupParams.skipFpga = 1

sysParams = AFE.systemParams

setupParams.fpgaRefClk = 245.76

AFE.systemStatus.loadTrims = 1

sysParams.FRef = 491.52

sysParams.FadcRx = 2949.12

sysParams.FadcFb = 2949.12

sysParams.Fdac = 2949.12 * 3

sysParams.rxEnable = [True,True,True,True]

sysParams.txEnable = [False,False,False,False]

sysParams.fbEnable = [False,False]

sysParams.enableDacInterleavedMode = False

sysParams.modeTdd = 0

sysParams.topLevelSystemMode = 'StaticTDDMode'

sysParams.RRFMode = 0 #4T4R2F TDD Non-Shared

sysParams.jesdSystemMode = [0,0]

sysParams.jesdLoopbackEn = 0

sysParams.LMFSHdRx =['12410', '12410', '12410', '12410']

sysParams.LMFSHdFb = ['12410', '12410']

sysParams.LMFSHdTx = ['12410', '12410', '12410', '12410']

sysParams.jesdTxProtocol = [0,0]

sysParams.jesdRxProtocol = [0,0]

sysParams.serdesFirmware = True

sysParams.jesdTxLaneMux = [0,1,4,5,2,3,6,7]

sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7]

sysParams.jesdRxRbd = [4, 4]

sysParams.jesdTxRbd = [1, 1]

sysParams.rxJesdTxScr = [False,False,False,False]

sysParams.fbJesdTxScr = [False,False]

sysParams.jesdRxScr = [False,False,False,False]

sysParams.rxJesdTxK = [32,32,32,32]

sysParams.fbJesdTxK = [32,32]

sysParams.jesdRxK = [32,32,32,32]

sysParams.ncoFreqMode = "FCW"

sysParams.txNco0 = [[7500,7500], [7500,7500], [7500,7500], [7500,7500]]

sysParams.rxNco0 = [[7500,7500],[7500,7500],[7500,7500],[7500,7500]]

sysParams.fbNco0 = [2600,2600] #FBA, FBC for NCO0

sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual

sysParams.numBandsFb = [0,0]

sysParams.numBandsTx = [0,0,0,0]

sysParams.ducFactorTx = [36,36,36,36]

sysParams.ddcFactorFb = [12,12]

lmkParams.pllEn = True #False

lmkParams.inputClk = 1474.56 #737.28

lmkParams.sysrefFreq = 7.68

lmkParams.lmkFrefClk = True

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")

logDumpInst.logFormat = 0x00

logDumpInst.rewriteFile = 1

logDumpInst.rewriteFileFormat4 = 1

device.optimizeWrites = 0

device.rawWriteLogEn = 1

sysParams.jesdABLvdsSync = 0

sysParams.jesdCDLvdsSync = 0

sysParams.rxJesdTxSyncMux = [0,0,0,0]

sysParams.fbJesdTxSyncMux = [0,0]

sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]

sysParams.syncLoopBack = True

sysParams.gpioMapping={

'H8': 'ADC_SYNC0',

'H7': 'DAC_SYNC0',

'N8': 'ADC_SYNC2',

'N7': 'ADC_SYNC3',

'H9': 'ADC_SYNC1',

'G9': 'DAC_SYNC1',

'N9': 'DAC_SYNC2',

'P9': 'DAC_SYNC3',

'P14':'GLOBAL_PDN',

'H12':'RXA_DSA_GAIN_1',

'N13':'RXA_DSA_GAIN_2',

'V5': ['TXCTDD','TXDTDD'],

'H12': ['RXATDD','RXBTDD'],

'R15': ['RXCTDD','RXDTDD']}

setupParams.skipLmk = False

AFE.initializeConfig()

lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq

lmkParams.lmkPulseSysrefMode = False

AFE.LMK.lmkConfig()

setupParams.skipLmk = True

AFE.deviceBringup()

AFE.TOP.overrideTdd(15,0,15)

AFE7950: Inquiry for Purchase and Technical Support – AFE7950 RF-Sampling Transceiver

M Arshad — Mon, 18 May 2026 06:48:34 GMT

Part Number: AFE7950

Dear Texas Instruments Team,

I hope you are doing well.

We are interested in purchasing the AFE7950 4-transmit, 6-receive RF-sampling transceiver for our upcoming project.

In this regard, we would appreciate it if you could provide the following information:

Availability and procurement process for the AFE7950 device.
Technical support availability for future communication regarding this device, preferably through online meetings, email support, or call assistance.
Confirmation whether there are any export restrictions, sales limitations, or regulatory requirements for supplying this device to Pakistan.

Your support and guidance in this matter will be highly appreciated. We look forward to your response.

Muhammad Arshad (Mr)

(Purchase Manager)

Shaheq Aljazeera Pvt ltd

Cell: +92-331-9994157

AFE7950EVM: Issue with programming NCO from PC

ABDCEF — Mon, 18 May 2026 05:50:33 GMT

Part Number: AFE7950EVM

we tried to program the AFE from latte.And we update NCO from latte,and it got updated. SO we want to replicate it from pc, So inorder to that, we wanted know what and all the SPI_WRITES are responsible for programming NCO of a particular channel .Here are the log files that are created for programming NCO of multiple channels from LATTE, from this what and all the SPI_Writes are responsible for program NCO of corresponding channel from PC . Please let us know if you need any further information .Thank you.
txA_8500.txt rxA_8500.txt

AFE7950EVM: AFE Bringing up from PC

ABDCEF — Fri, 15 May 2026 06:23:56 GMT

Part Number: AFE7950EVM

We are facing issue while bringingup Afe with Hardware from PC. We got latte scripts from TI people, we are using an external 1500MHZ clock at LMK_CLK in , and while programming AFE7950EVM with latte we are able to get the locks, and proper rf siganl . And there is other signals in the VIO named as sysref_realign_count. It's value is changing accroding to the image attcahed below.

And i am attching the log file created from LATTE aslo . Afe79xxPg1 (2).txt

So by using the same log file we are programming AFE from PC by passing LATTE, but at that time we are getting a different values for the sysref_realign_count.

And along with that if we are trying to give a RF signal with some offset from our NCO then DAC is producing multiple unwanted peaks. Please let us know why this is happening. Thank you.

SN7400: Can 54HCT138 3 bit to 8 bit decoder survive storage at -65C degrees

Jerold Lee — Wed, 13 May 2026 20:10:54 GMT

Part Number: SN7400
Other Parts Discussed in Thread: SN54HCT138

We plan to use the SN54HCT138 3-bit-to-8-bit decoder to convert 3 bits into 8 bits to drive PIN switches (12 mA). Is there an evaluation board available, and can this part withstand -65 °C storage? If not, can you recommend a part?

AFE7920: New version of SBAU337_13th_May_2020 for AFE79XX chips

Danilo A. — Tue, 12 May 2026 13:43:49 GMT

Part Number: AFE7920

Hi Team,

Posting on behalf of our customer.

I need support with chip documentation. I was wondering if there is a new version SBAU337_13th_May_2020 for AFE79XX chips. The one provided in the secure resources seems to be outdate and does not match the provided library macro opcodes.

I'am using CAFE79XX_V2p5 library source code and it contains macro interface operation codes which are not documented in the SBAU337_13th_May_2020. Additionally, the documentation says that it is a draft. So i was wondering if there may be a new version of the documentation.

Regards,

Danilo

AFE7950: AFE7950 RF Output

Garima Dubey — Tue, 12 May 2026 12:38:25 GMT

Part Number: AFE7950

Hi TI Team,

What are the recommended settings for AFE configuration in lattice script to ensure maximum receive power and maximum transmit power at 9.5GHz channel.

AFE7950EVM: AFE7950EVM+ZCU102 SPI Configuration

Paolo Artieri — Mon, 11 May 2026 15:42:08 GMT

Part Number: AFE7950EVM

Hi All

I have the AFE7950EVM board connected to a ZCU102.
Until now I used the LatteGUI tool to configure LMK and AFE via SPI peripheral.
I see the SBAU412A bringup guide to configure LMK and AFE via SPI from FMC ZCU102 connector.
I did the following modification inside the picture:

I use the Vivado bd for SPI controller and adds the 5 SPI pins only:
- clock, datai, datao, sen0, sen1

I generate the Vitis project and see that SPI works fine, LMK was configured and D3 led is on, AFE was configured and see sync TX/RX high on ILA inside HardwareManager of Vivado.
There is a problem:
- no RF signal can see at the output with spectrum analyzer for TX, no RX signal also
- power current of the AFE is less then one half
Usually its about 2.5A with 6Volt when configure with LatteGUI.
In this case where a configure with FMC SPI power corrent is about 1A, but I dont understand why.

Every spi register file were geerate with LatteGUI for Vitis application:
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x21 #0x00
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1
lmklogDumpInst = mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1_LMK.txt")
lmklogDumpInst.logFormat = 0x1
lmk.logClassInst = lmklogDumpInst
lmk.rawWriteLogEn = 1

What is the reason about this problem?

Thanks

AFE7903: Access to full datasheet - resolved

M Parsons — Mon, 11 May 2026 10:34:57 GMT

Part Number: AFE7903

Hi, on the 06/05/26 I requested full access to the AFE79XX-WI-DESIGN and AFE79XX-HSC-DESIGN datasheets. The WI version was approved the next day, but I am still waiting for approval for the AFE79XX-HSC-DESIGN.

I was hoping to check that the AFE79XX-HSC-DESIGN request hadn't accidentally been missed?

The datasheet has now been released and my issue has been resolved. Thank you.

AFE8030: Transmitter, receiver RF impedance

Gabor Negyesi — Mon, 11 May 2026 09:40:25 GMT

Part Number: AFE8030

I intend to use the AFE8030 octal transceiver. The RF ports impedance is not given in the datasheet. Only that it has -12dB return loss with matching. There are some examples for 700MHz and 1800MHz, but I want to use it at different IF frequency, the reciever at 4GHz IF and the transmitter at 4.8GHz IF. Do you have suggested matching network for these IF frequencies? Or do you have S-parameter file for the full frequency range so that we could design a custom matching?

Thank you for your help.

Gabor Negyesi

AFE7950EVM: Downloading TI-JESD204-IP

Jack Christman — Mon, 11 May 2026 04:17:35 GMT

Part Number: AFE7950EVM
Other Parts Discussed in Thread: TI-JESD204-IP,

Hello,

I am working on a development project with the AFE7950EVM and a ZCU102. We are a US based company working on an SDR application that will utilize the main chips from the above eval kits. We had attempted to download the TI-JESD204-IP Firmware, but access was denied and we were pointed to contacting support. May we get clarification on why the denial occurred? We are hoping to clear up any concerns that resulted in the denial.

AFE7728D: Bypass RFLO after DAC of AFE7728D

Tiến Đức — Mon, 11 May 2026 03:01:49 GMT

Part Number: AFE7728D

Hi everyone,

Now i'm working with AFE7728D but i want only use the data directly after DAC, is possible to turn off or bypass the RRLO after DAC ?

Thank you very much./.

AFE7920EVM: How to modify the configuration file of Latte to change the original 491Mhz sampling configuration to 983Mhz sampling and the bandwidth to 450Mhz?

Yamada Taro — Mon, 11 May 2026 02:33:29 GMT

Part Number: AFE7920EVM
Other Parts Discussed in Thread: AFE7920

Thanks to TI's last provision of configuration files of Latte last time. I have successfully run the environment with a sampling rate of 491.52Mhz before. But what modifications do I need to make to the configuration file and the JESD IP TI provided last time if I want to run in an environment with 983.04Mhz and 450M bandwidth?
I am using AFE7920 and ZCU102.
Taro

AFE8192: AFE8192 design document

Eddie Liao — Fri, 08 May 2026 01:05:13 GMT

Part Number: AFE8192

Hi Sir

Do you have full design document of AFE8192? Could you provide it to me, please?

Best regards,

Eddie

AFE7900: TI IP supported in newer versions of Vivado

SM — Thu, 07 May 2026 08:24:55 GMT

Part Number: AFE7900

Hello,

We are seeing the following error:

TI_204c_IP_xilinx.svp cannot decrypt IEEE-1735 envelope:
When upgrading a 2020.1 project to 2024.1 we are getting the following error:
[#UNDEF] Cannot decrypt IEEE-1735 envelope: key value doesn't match key name "xilinxt_2017_05" (perhaps the public key was incorrect at encryption time).

Thank you for your time,

AFE7950: AFE7950 ZCU102 Contractor

JT Miller — Wed, 06 May 2026 15:34:29 GMT

Part Number: AFE7950

We are interested in migrating a TI-supplied AFE7950EVM reference design to a custom ZCU102 design. This would involve replacing the Microblaze with the A53 and refining the 80k SPI register writes with only the necessary writes.

Does TI have any list of contractors which could support this work?

LMX2695SEPEVM: Is there a datasheet available for the LMX2624 & LMX2695-SEP

ken mason — Wed, 06 May 2026 13:54:08 GMT

Part Number: LMX2695SEPEVM
Other Parts Discussed in Thread: LMX2624-SP, LMX2695-SEP, LMX2595

In the 2026 TI Space Products Guide there is mention of the LMX2624-SP & LMX2695-SEP (page 16).

I can find the LMX2624-SP datasheet but not the LMX2695-SEP, what is the difference?

How does the LMX2695-SEP differ from the LMX2595, is there any radiation data on the LMX2595?

AFE7950EVM: Unable to program AFE

Varshini Narayana — Wed, 06 May 2026 05:40:44 GMT

Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7900, LMK04828

I have pasted LMKProgram.py program. My issue will be written in next point.(Note: LMK is getting programmed and I am getting qpll acknowledgement)
I am trying to program Afe but i am getting follwoing errors (AFE is not getting programmed)

#======

#Executing .. AFE7900/NDET_7900/program_AFE.py

#Start Time 2026-05-06 10:43:04.027000

The External Sysref Frequency should be an integer factor of: 3.84MHz

2T2R1F Number: 0

Valid Configuration: True

laneRateRx: 9830.4

laneRateFb: 9830.4

laneRateTx: 9830.4

2T2R1F Number: 1

Valid Configuration: True

laneRateRx: 9830.4

laneRateFb: 9830.4

laneRateTx: 9830.4

LMK and FPGA Configured.

DONOT_OPEN_Atharv_FULL - Device registers reset.

chipType: 0xa

chipId: 0x78

chipVersion: 0x11

AFE Reset Done

Fuse farm load autoload done successful

No autload error

Fuse farm load autoload done successful

No autload error

AFE MCU Wake up done and patch loaded.

PLL Locked

AFE PLL Configured.

AFE SerDes Configured.

AFE Digital Chains configured.

AFE TX Analog configured.

AFE RX Analog configured.

AFE FB Analog configured.

AFE JESD configured.

AFE AGC configured.

AFE GPIO configured.

Sysref Read as expected

###########Device DAC JESD-RX 0 Link Status###########

Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.

CS State TX0: 0b00000000 . It is expected to be 0b10101010

FS State TX0: 0b00000000 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 0; Alarms: 0x0

###################################

###########Device DAC JESD-RX 1 Link Status###########

Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.

CS State TX0: 0b00000000 . It is expected to be 0b10101010

FS State TX0: 0b00000000 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 1; Alarms: 0x0

###################################

AFE Configuration Complete

#Done executing .. AFE7900/NDET_7900/program_AFE.py

#End Time 2026-05-06 10:44:53.156000

#Execution Time = 109.128999949 s

#================ ERRORS:10, WARNINGS:0 ================#

#================ LMK Program ================#

'''
Validation : AFE79xx Library Version
v1.67, v1.74
Case RX TX FB CLK Notes
---- ----------------- ----------------- ----------------- ----------- ------------
1 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in interleaved mode
SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M

2 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in straight mode
SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
'''
setupParams.skipFpga = 1
sysParams = AFE.systemParams
setupParams.fpgaRefClk = 245.76#184.32#
AFE.systemStatus.loadTrims = 1

sysParams.fbEnable = [False]*2
sysParams.externalClockTx = False
sysParams.externalClockRx = False
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4

sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd = 0
# 0- Single TDD Pin for all Channels
# 1- Separate Control for 2T/2R/1F
# 2- Separate Control for 1T/1R/1F

sysParams.RRFMode = 0 #4T4R2F FDD mode
sysParams.jesdSystemMode = [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
#SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx1-rx1-rx1-rx1
#SystemMode 4: 1F ; fb-fb-fb-fb
#SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
#SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1

sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx = ["44210","44210","44210","44210"]
# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdTxProtocol = [0,0]
sysParams.jesdRxProtocol = [0,0]
sysParams.serdesFirmware = True # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2T Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity = [True, True, False, False, True, True, False, False]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,7,6] #[0,1,2,3,4,5,7,6]
# Enter which lanes you want in each location.
# Note that across 2R Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesRxLanePolarity = [True, True, True, True, False, False, False, False]
sysParams.jesdRxRbd = [4, 4]

sysParams.rxJesdTxScr = [False]*4
sysParams.fbJesdTxScr = [False]*2
sysParams.jesdRxScr = [False]*4

sysParams.rxJesdTxK = [32]*4
sysParams.fbJesdTxK = [32]*2
sysParams.jesdRxK = [16]*4

sysParams.ncoFreqMode = "FCW"

sysParams.txNco0 = [[3800,1800], #Band0, Band1 for TxA for NCO0
[1000,1800], #Band0, Band1 for TxB for NCO0
[3800,1800], #Band0, Band1 for TxC for NCO0
[1800,1800]] #Band0, Band1 for TxD for NCO0

sysParams.rxNco0 = [[3800,1800], #Band0, Band1 for RxA for NCO0
[1000,1800], #Band0, Band1 for RxB for NCO0
[3800,1800], #Band0, Band1 for RxC foQr NCO0
[1800,1800]] #Band0, Band1 for RxD for NCO0

sysParams.fbNco0 = [1800,1800] #FBA, FBC for NCO0
sysParams.fbNco1 = [1800,1800] #FBA, FBC for NCO1
sysParams.fbNco2 = [1800,1800] #FBA, FBC for NCO2
sysParams.fbNco3 = [1800,1800] #FBA, FBC for NCO3

sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual
sysParams.numBandsFb = [0,0]
sysParams.numBandsTx = [0,0,0,0]

sysParams.ddcFactorRx = [6]*4 # DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb = [6]*4
sysParams.ducFactorTx = [24]*4

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn = True#False#False
lmkParams.inputClk = 1474.56#737.28
lmkParams.sysrefFreq = 2949.12/1024
lmkParams.lmkFrefClk = True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
#lmklogDumpInst = mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxpg1.txt")
logDumpInst.logFormat = 0x21
#logDumpInst.logFormat = 0x0f
logDumpInst.rewriteFile = 1
lmk.logClassInst =logDumpInst
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1
lmk.rawWriteLogEn = 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = 0
sysParams.jesdCDLvdsSync = 0
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True

sysParams.defaultRxDsa =[0,0,0,0]
sysParams.defaultFbDsa = [0,0]
sysParams.defaultTxDsa =[0,0,0,0]

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns.
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent

## The following parameters sets up the GPIOs
sysParams.gpioMapping={
'H8': 'ADC_SYNC0',
'H7': 'DAC_SYNC0',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'ADC_SYNC1',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}

#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
setupParams.skipLmk = False

AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()

AFE7950: restricted data sheet

Lauren Watkins — Tue, 05 May 2026 20:58:05 GMT

Part Number: AFE7950

Please send information on the serial interface to the AFE7950 converter and the serial chip - to include layout

AFE7950: data sheet (restricted)

Lauren Watkins — Tue, 05 May 2026 20:53:41 GMT

Part Number: AFE7950

I am looking for information on the serial interface and overflow flag for the AFE7950 A/D. The deveice is designed into a product and we need to make modification to the product

AFE7950: TI-JESD204-IP, 3 RX and 2 TX Mapped to One AMD Quad Transceiver

Scott Geaghan — Tue, 05 May 2026 17:27:12 GMT

Part Number: AFE7950

Hello,

I’m using your TI-JESD204c IP on a Versal VCK190 Evaluation Platform. I have a configuration with 3 RX lanes and 2 TX lanes. All lanes run at a line rate of 24.75 Gb/sec with 64b66b encoding. All lanes use a reference clock of 375 MHz. I need to map the design to a single quad transceiver on the FPGA. This configuration maps to what we believe to be a valid operating mode on the TI AFE7950.

Everything works in QuestaSim if I use the following configuration:

1. One instantiation of the TI IP configured for simplex TX with 2 lanes
2. One instantiation of the TI IP configured for simplex RX with 3 lanes
3. One instantiation of the TI IP configured for simplex RX with 2 lanes (simulation only, connects to #1)
4. One instantiation of the TI IP configured for simplex TX with 3 lanes (simulation only, connects to #2)

#1 and #2 need to synthesize, and #3 and #4 are for simulation only. #1, #2, #3, and #4 are all separate TI IP simplex instantiations that use separate simplex instantiations of the Versal transceiver IP.

I can build an FPGA with #1 and #2, but Vivado won’t let me map #1 and #2 to the same quad transceiver, which is a requirement for my company.

I created a new Versal transceiver that contains two interfaces. Interface zero is simplex RX with 3 lanes. Interface one is simplex TX with 2 lanes. In other words, I combined #1 and #2 into one Versal transceiver instantiation. Let’s call this the duplex instantiation with asymmetrical TX (2 lanes) and RX (3 lanes). It is my understanding that creating one Versal transceiver with one simplex RX interface (3 lanes) and one simplex TX interface (2 lanes), all using the same line rate and reference clock rate, will allow me to map the transceiver to a single quad transceiver on the FPGA. I’m still instantiating #3 and #4 for simulation.

When I simulate the duplex transceiver, the duplex receiver locks on the 3 RX lanes and receives data. However, #3 never locks on the 2 RX lanes.

Can you please help me get this working?

One thing that confuses me is that your Verilog header file (jesd_link_params.vh) allows one to define NUMBER_OF_RX_LANES and NUMBER_OF_TX_LANES. I would like NUMBER_OF_RX_LANES to be 3 and NUMBER_OF_TX_LANES to be 2. However, your wrapper module (mgt_64b66b_wrap) only defines NUM_LANES.

I want to instantiate a Versal transceiver inside mgt_64b66b_wrap() that has (NUMBER_OF_RX_LANES == 3) and (NUMBER_OF_TX_LANES == 2). Can this be done? If not, is there some other way to accomplish what I need to do?

Regards,
Scott Geaghan
Assurance Technology Corporation

AFE7900: Custom hardware: Minimal FTDI/Latte interface requirements

Renan Santos Adriano — Tue, 05 May 2026 16:15:58 GMT

Part Number: AFE7900

Hello Experts,

I am designing custom hardware (Software Defined Radio) using the AFE7900. For the first development phase, I would like to configure the AFE7900 and the LMK clocking device directly from Latte, similar to the AFE7900EVM flow.

I reviewed the AFE7900EVM schematic and noticed that the onboard FT4232H connects to several interfaces, including AFE SPIA, additional SPI interfaces, UART, CPLD SPI, I2C, and an AFE JTAG connection. I would like to simplify this on my custom board and only keep the interfaces required for Latte-based configuration.

My current understanding is that Latte mainly needs:

AFE SPIA
LMK SPI
AFE reset
optionally UART for FPGA/debug purposes

I have the following questions:

CPLD usage on the EVM
Is the CPLD actually required by Latte during normal AFE7900 and LMK configuration?
From my current analysis, it looks like the CPLD on the EVM is not required for the basic Latte configuration flow, but I would like to confirm this.
FTDI JTAG connection to the AFE7900
The EVM routes one FT4232H channel to the AFE JTAG pins.
Is this JTAG interface used by Latte when configuring the AFE7900, loading patches, or initializing the device?
Or is it only intended for TI internal debug, boundary scan, or factory/test purposes?
FTDI EEPROM contents / identification
What exactly is programmed into the FTDI EEPROM on the AFE7900EVM (U12)?
Does Latte depend on a specific EEPROM configuration, such as product description, serial number, channel mode, or FTDI interface assignment?
Can I use a standard FTDI module, for example the FT4232H-56Q MINI MDL, for Latte access if it has the same EEPROM device, or does it need to be programmed with EVM-specific contents?
Minimal interface for custom hardware
For a custom AFE7900 board that should initially be configurable from Latte, would the following interface be sufficient?
- FTDI channel for AFE SPIA
- FTDI channel for LMK SPI
- Reset control for the AFE7900
- optional UART/debug connection
- no AFE JTAG
- no CPLD SPI, assuming no CPLD is used on the custom board

Could you please confirm the minimum required FTDI/Latte interface for custom hardware?

The goal is to keep the custom PCB as simple as possible while still being able to use Latte during early bring-up and development.

Best regards,
Tobias

AFE7900EVM: AFE7900EVM: All 4 TX Channels Not Working Simultaneously with JESD204B

Ahmad Naveed — Fri, 01 May 2026 11:51:01 GMT

Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7950

Hi,

I want to obtain DAC output from all four TX channels simultaneously, but the board only outputs on max two channels.

Setup:

The AFE7900EVM is connected to an Avnet UltraZed-EV carrier card with a 7EV SOM. The Xilinx JESD204 PHY, along with JESD204 IP cores, is used to transmit and receive data. The IP parameters are as follows:

Lanes per link: 4
Octets per frame: 4
Frames per multiframe: 32
Line rate: 9.8304 Gbps
Reference clock: 245.76 MHz

Physically, the first four lanes (0, 1, 2, and 3) are connected to the AFE first 4 Lanes, all operating at the same IF within 10 MHz, depending on the DDS configuration. All four lanes have been verified to work independently by connecting each lane to the same channel one at a time. Each produces the expected output signal.

I am using a single link (Band_0) for all channels. Each channel (TXA through TXD) works correctly when tested independently. However, when connecting the lanes one-to-one with Band_0 across all TX channels, I have tested various configurations of the lane mux and data mux. The signal appears on only one or two channels simultaneously, but never on any third channel.

The data is driven after TX sync is asserted and is shared across all four channels. The same behavior has also been observed on an 11EG carrier card with an AFE7950.

I have attached the Latte script I am using to program the AFE board. With this configuration, only TXC outputs the signal. (The NCO for TXB is set out of band due to limitations of my spectrum analyzer; however, it should still produce an attenuated version of the signal.)

You may ignore the RX settings for now, as they are not the main concern.

setupParams.skipFpga 				= 1
sysParams							=	AFE.systemParams
#setupParams.fpgaRefClk 				= 122.88
setupParams.fpgaRefClk 				= 245.76	
AFE.systemStatus.loadTrims			= 1

sysParams.FRef                    	= 491.52
sysParams.FadcRx                  	= 2949.12
sysParams.FadcFb				  	= 2949.12
sysParams.Fdac                    	= 2949.12*3
# sysParams.Fdac                    	= 8847.36
#sysParams.FRef                    	= 500
#sysParams.FadcRx                  	= 3000
#sysParams.FadcFb				  	= 3000
#sysParams.Fdac                    	= 9000

#sysParams.rxEnable                  =   [True,False,False,False]
sysParams.rxEnable		            =	[True,True,True,True]
sysParams.fbEnable		            =	[True,True]
sysParams.txEnable                  =   [True,True,True,True]
sysParams.enableDacInterleavedMode	= False 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
#sysParams.jesdSystemMode			= [3,3]
sysParams.jesdSystemMode			= [0,0]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
#sysParams.LMFSHdRx                	=['12410', '12410', '12410', '12410']
sysParams.LMFSHdRx                	=['12410', '12410', '12410', '12410']
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["12410","12410"]
# sysParams.LMFSHdTx                	= ["24410","24410","24410","24410"]
sysParams.LMFSHdTx                	= ["12410","12410","12410","12410"]
# sysParams.LMFSHdTx                	= ["12410","12410","12410","12410"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,4,5,6,2,3,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
# sysParams.jesdRxLaneMux				= [0,4,1,5,2,6,3,7]	
# sysParams.jesdRxLaneMux             = [0,1,4,5,2,3,6,7]
sysParams.jesdRxLaneMux             = [0,4,1,5,2,6,3,7]
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
												
sysParams.dacDataMuxEn      =  False #to enable datamux												
# sysParams.txDataMux					= [6,7,0,1,4,5,2,3]
# sysParams.txDataMux					= [0,4,1,5,2,6,3,7]
# sysParams.txDataMux					= [6,7,2,3,4,5,0,1]

sysParams.adcDataMuxEn = False
# sysParams.rxDataMux =  [0,1,2,3,4,5,6,7]
# sysParams.rxDataMux =  [6,7,4,5,0,1,2,3]
#sysParams.rxDataMux =  [4,5,6,7,0,1,2,3]    # working
# sysParams.rxDataMux =  [6,7,4,5,0,1,2,3]  # working
#sysParams.rxDataMux =  [2,3,6,7,0,1,4,5]

sysParams.jesdRxRbd					= [4, 4]
sysParams.jesdTxRbd					= [1, 1]

sysParams.rxJesdTxScr				= [False,False,False,False]
sysParams.fbJesdTxScr				= [False,False]
sysParams.jesdRxScr					= [False,False,False,False]

sysParams.rxJesdTxK					= [32,32,32,32]
sysParams.fbJesdTxK					= [32,32]
sysParams.jesdRxK					= [32,32,32,32]

#sysParams.ncoFreqMode 				= "1KHz"
sysParams.ncoFreqMode 				= "FCW"	
# sysParams.txNco0					= 	[[362.32,362.32],		#Band0, Band1 for TxA for NCO0
# 										[362.32,362.32],        #Band0, Band1 for TxB for NCO0
# 										[362.32,362.32],        #Band0, Band1 for TxC for NCO0
# 										[362.32,362.32]]       #Band0, Band1 for TxD for NCO0

sysParams.rxNco0					= 	[[120,120],		#Band0, Band1 for TxA for NCO0
										[1820,1820],        #Band0, Band1 for TxB for NCO0
										[2118,2118],        #Band0, Band1 for TxC for NCO0
										[520,520]]       #Band0, Band1 for TxD for NCO0


sysParams.txNco0					= 	[[120,120],		#Band0, Band1 for RxA for NCO0
										[1820,1820],        #Band0, Band1 for RxB for NCO0
										[2118,2118],        #Band0, Band1 for RxC for NCO0#
										[520,520]]        #Band0, Band1 for RxD for NCO0

# sysParams.txNco1					= 	[[262.32,262.32],		#Band0, Band1 for TxA for NCO0
# 										[262.32,262.32],        #Band0, Band1 for TxB for NCO0
# 										[262.32,262.32],        #Band0, Band1 for TxC for NCO0
# 										[262.32,262.32]]        #Band0, Band1 for TxD for NCO0
# 
# 
# sysParams.rxNco0					= 	[[120,120],		#Band0, Band1 for RxA for NCO0
# 										[120,120],        #Band0, Band1 for RxB for NCO0
# 										[120,120],        #Band0, Band1 for RxC for NCO0#
# 										[120,120]]        #Band0, Band1 for RxD for NCO0										
										

#sysParams.rxNco0					= 	[[200,200],		 #Band0, Band1 for RxA for NCO0
#									[200,200],        #Band0, Band1 for RxB for NCO0
#									[200,200],        #Band0, Band1 for RxC for NCO0
#									[200,200]]        #Band0, Band1 for RxD for NCO0


sysParams.fbNco0					= 	[370,1500]			#FBA, FBC for NCO0

sysParams.fbDataMux                 = [0,1]
sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

#sysParams.ddcFactorRx             	= [24,24,24,24]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorRx             	= [12,12,12,12]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [12,12]
# sysParams.ducFactorTx             	= [24,24,24,24]
sysParams.ducFactorTx             	= [36,36,36,36]
#sysParams.ducFactorTx             	= [72,72,72,72]

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
# lmkParams.sysrefFreq				=	3.84
# lmkParams.sysrefFreq				=	1.92
lmkParams.sysrefFreq				=	0.48
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x00
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 0
sysParams.jesdCDLvdsSync			= 0
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'DAC_SYNC0',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'ADC_SYNC1',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'N13': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'H12': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
		

## Initiates LMK04828 and AFE79xx Bring-up
setupParams.skipLmk	=	False

AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
## Initiates AFE79xx Bring-up
setupParams.skipLmk	=	True
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)
# AFE.JESD.ADCJESD[0].adcRampTestPattern(0,1,0)
# AFE.JESD.ADCJESD[0].adcRampTestPattern(1,1,0)
# AFE.JESD.ADCJESD[1].adcRampTestPattern(0,1,0)
# AFE.JESD.ADCJESD[1].adcRampTestPattern(1,1,0)

#AFE.JESD.DACJESD[0].dacJesdConstantTestPatternValue(1,0,0,16384,0)
#AFE.JESD.DACJESD[0].dacJesdConstantTestPatternValue(1,1,0,16384,0)

#AFE.JESD.DACJESD[1].dacJesdConstantTestPatternValue(1,0,0,16384,0)
#AFE.JESD.DACJESD[1].dacJesdConstantTestPatternValue(1,1,0,16384,0)

Thanks & regards,
Ahmad