RF & microwave forum - Recent Threads

AFE7920EVM: How to modify the configuration file of Latte to change the original 491Mhz sampling configuration to 983Mhz sampling and the bandwidth to 450Mhz?

Yamada Taro — Mon, 11 May 2026 02:33:29 GMT

Part Number: AFE7920EVM

Thanks to TI's last provision of configuration files of Latte last time. I have successfully run the environment with a sampling rate of 491.52Mhz before. But what modifications do I need to make to the configuration file and the JESD IP TI provided last time if I want to run in an environment with 983.04Mhz and 450M bandwidth?
I am using AFE7920 and ZCU102.
Taro

RE: AFE7920EVM: How to modify the configuration file of Latte to change the original 491Mhz sampling configuration to 983Mhz sampling and the bandwidth to 450Mhz?

Yamada Taro — Tue, 12 May 2026 02:43:07 GMT

Hi Aman,

In fact, I have tried adjusting the parameters you mentioned, but they did not work. Thank you very much for being willing to help me adjust the parameters. Can you tell me your email?

Thanks!

Taro

RE: AFE7920EVM: How to modify the configuration file of Latte to change the original 491Mhz sampling configuration to 983Mhz sampling and the bandwidth to 450Mhz?

Aman Thombre — Tue, 12 May 2026 01:40:10 GMT

Hi Taro,

In order to change the sampling rate from 491.52 MHz to 983.04 MHz, we must change the decimation and interpolation factors for the DAC and ADC. The sampling rate is given by Fs / DDC_factor for the ADC side and Fs / DUC_factor for the DAC side. So, we can simply half the DDC and DUC factors.

Note that changing the sampling rate will also affect the JESD rate (doubling the IQ rate will double the JESD lane rate). Therefore, you will either need to adjust the lane rate on ZCU102 or adjust the LMFS settings to use more JESD lanes to maintain the same lane rate. If you choose to change the LMFS settings, we will also need to update these settings in the AFE configuration.

I can help you with adjusting these parameters in the AFE configuration. Could you kindly provide me with the following?

AFE configuration file used in Latte (this will by a Python file with .py extension)
Desired JESD lane rate
Desired JESD LMFS settings
Desired JESD lanes to use

If you would prefer to share these files and continue this conversation privately, please let me know and I can get in touch with you via email.

Thanks!

Aman

AFE8030: Transmitter, receiver RF impedance

Gabor Negyesi — Mon, 11 May 2026 09:40:25 GMT

Part Number: AFE8030

I intend to use the AFE8030 octal transceiver. The RF ports impedance is not given in the datasheet. Only that it has -12dB return loss with matching. There are some examples for 700MHz and 1800MHz, but I want to use it at different IF frequency, the reciever at 4GHz IF and the transmitter at 4.8GHz IF. Do you have suggested matching network for these IF frequencies? Or do you have S-parameter file for the full frequency range so that we could design a custom matching?

Thank you for your help.

Gabor Negyesi

RE: AFE8030: Transmitter, receiver RF impedance

Benjamin Uhing — Mon, 11 May 2026 21:44:41 GMT

Gabor,

I'm connecting you with our marketing engineer Simran. We have S-parameter impedance measurements, but we'd like to discuss your use case before sharing.

Thanks for reaching out,

Ben

AFE7950EVM: AFE7950EVM+ZCU102 SPI Configuration

Paolo Artieri — Mon, 11 May 2026 15:42:08 GMT

Part Number: AFE7950EVM

Hi All

I have the AFE7950EVM board connected to a ZCU102.
Until now I used the LatteGUI tool to configure LMK and AFE via SPI peripheral.
I see the SBAU412A bringup guide to configure LMK and AFE via SPI from FMC ZCU102 connector.
I did the following modification inside the picture:

I use the Vivado bd for SPI controller and adds the 5 SPI pins only:
- clock, datai, datao, sen0, sen1

I generate the Vitis project and see that SPI works fine, LMK was configured and D3 led is on, AFE was configured and see sync TX/RX high on ILA inside HardwareManager of Vivado.
There is a problem:
- no RF signal can see at the output with spectrum analyzer for TX, no RX signal also
- power current of the AFE is less then one half
Usually its about 2.5A with 6Volt when configure with LatteGUI.
In this case where a configure with FMC SPI power corrent is about 1A, but I dont understand why.

Every spi register file were geerate with LatteGUI for Vitis application:
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x21 #0x00
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1
lmklogDumpInst = mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1_LMK.txt")
lmklogDumpInst.logFormat = 0x1
lmk.logClassInst = lmklogDumpInst
lmk.rawWriteLogEn = 1

What is the reason about this problem?

Thanks

AFE7903: Access to full datasheet

Mae Parsons — Mon, 11 May 2026 10:34:57 GMT

Part Number: AFE7903

Hi, on the 06/05/26 I requested full access to the AFE79XX-WI-DESIGN and AFE79XX-HSC-DESIGN datasheets. The WI version was approved the next day, but I am still waiting for approval for the AFE79XX-HSC-DESIGN.

I was hoping to check that the AFE79XX-HSC-DESIGN request hadn't accidentally been missed?

Thanks,

Mae

AFE7950EVM: Downloading TI-JESD204-IP

Jack Christman — Mon, 11 May 2026 04:17:35 GMT

Part Number: AFE7950EVM

Hello,

I am working on a development project with the AFE7950EVM and a ZCU102. We are a US based company working on an SDR application that will utilize the main chips from the above eval kits. We had attempted to download the TI-JESD204-IP Firmware, but access was denied and we were pointed to contacting support. May we get clarification on why the denial occurred? We are hoping to clear up any concerns that resulted in the denial.

AFE7728D: Bypass RFLO after DAC of AFE7728D

Tiến Đức — Mon, 11 May 2026 03:01:49 GMT

Part Number: AFE7728D

Hi everyone,

Now i'm working with AFE7728D but i want only use the data directly after DAC, is possible to turn off or bypass the RRLO after DAC ?

Thank you very much./.

AFE7900: TI IP supported in newer versions of Vivado

SM — Thu, 07 May 2026 08:24:55 GMT

Part Number: AFE7900

Hello,

We are seeing the following error:

TI_204c_IP_xilinx.svp cannot decrypt IEEE-1735 envelope:
When upgrading a 2020.1 project to 2024.1 we are getting the following error:
[#UNDEF] Cannot decrypt IEEE-1735 envelope: key value doesn't match key name "xilinxt_2017_05" (perhaps the public key was incorrect at encryption time).

Thank you for your time,

RE: AFE7900: TI IP supported in newer versions of Vivado

David Chaparro — Fri, 08 May 2026 18:45:25 GMT

Hi SM,

In the TI204c IP secure folder there are two different version of the encrypted IP to support different versions of Vivado. Can you please download the latest IP version and use the IP core from the folder named "Vivado_2022_and_Newer"?

Regards,

David Chaparro

RE: AMC7908EVM: AMC7908EVM Sparked and blew up

Nathan Kidd — Fri, 08 May 2026 17:50:58 GMT

In both these cases, I had the output wired into an oscilliscope.

Nathan

AMC7908EVM: AMC7908EVM Sparked and blew up

Nathan Kidd — Thu, 23 Apr 2026 00:32:48 GMT

Part Number: AMC7908EVM

Hello,

I broke an AMC7908EVM today, and I'm trying to understand what happened so it doesn't happen again. Here are the facts:

- I was working with an AMC7908EVM and conducting experiments involving the DRVEN0 pin.

- VIO was powered via USB, but VCCA was not powered (it was connected to a power supply which had its output disabled by accident).

- J23 was left unjumpered, so DRVEN0 was not connected to the on‑board FTDI GPIO and was instead being driven externally (unintentional, I actually was trying to use the FTDI to drive the DRVEN0).

- A function generator was connected directly to the DRVEN0 pin, supplying a 2 V square wave. During this condition, I was pulsing DRVEN0 without any VCCA supply present.

- Shortly after applying this stimulus, the AMC7908 device on the EVM Sparked and became unresponsive. All registers returned 0xFF and there was no output. The FTDI chip was still fine.

Could you please help me understand what might have happened? From what I can tell, I accidentally created an erroroneous power supply condition where I started pulsing a digital pin before supplying power.

Thanks!

Nathan

AFE8192: AFE8192 design document

Eddie Liao — Fri, 08 May 2026 01:05:13 GMT

Part Number: AFE8192

Hi Sir

Do you have full design document of AFE8192? Could you provide it to me, please?

Best regards,

Eddie

RE: AFE8192: AFE8192 design document

Kang Hsia — Fri, 08 May 2026 02:35:00 GMT

Hi Eddie,

Could you please request the information from the link below? Thanks!

https://www.ti.com/drr/opn/AFE81XX-WI-DESIGN

-Kang

RE: AMC7908EVM: AMC7908EVM Sparked and blew up

Erin Bowrie — Thu, 07 May 2026 20:28:42 GMT

Hi Nathan,

I don't see anything particularly wrong with your setup; Do note that by default, the ADC starts in Auto conversion mode, so you won't see the "ADC_BUSY" flag in the gen status register go low once you trigger the ADC.

Are your output pins floating or tied to a PA when you're running this test? I'm still not seeing sparking when I use your setup, but my pin is floating. If you are using a PA, there may be some play between the PA gate and the device.

Thanks,
Erin

RE: AMC7908EVM: AMC7908EVM Sparked and blew up

Nathan Kidd — Thu, 07 May 2026 00:56:57 GMT

Here is the series of commands I give. These are taken out of context, so this is not representative of the program I have, but is representative of the order in which all the commands are issued.

I'll note that this does work (when the power supply is on, of course). The idea is to do the following:

1. Initialize

2. Set gate voltage

3. Loop a,b,c 5 times

3.a. Turn on gate - *pause*

3.b. Take current measurement

3.c. Turn off gate - *pause*

4. Do calculations and pause

5. Repeat 2, 3, 4 as desired

Somewhere in step 3 it sparked, it never reached step 4.

Initialization:

1. chip_id = read_register_paged(_GLOBAL_PAGE, _CHIP_ID_REGISTER)

2. chip_ver = read_register_paged(_GLOBAL_PAGE, _CHIP_VER_REGISTER)

3. update_paged_register(

_DAC_CONFIG_PAGE, _DAC_CFG_REGISTER,

lambda v: _set_bit(v, _DACA_BIPOLAR_BIT, False)

)

4. update_paged_register(

_GLOBAL_PAGE, _PWR_EN_REGISTER,

lambda v: _set_bit(_set_bit(v, _PWR_EN_DACA0_BIT, True), _PWR_EN_DACA1_BIT, True)

)

5. update_paged_register(

_GLOBAL_PAGE, _DRVEN_SW_EN_REGISTER,

lambda v: _set_bit(_set_bit(v, _DRVEN_SW_EN_DACA0_BIT, True), _DRVEN_SW_EN_DACA1_BIT, True)

)

6. update_paged_register(

_DAC_CONFIG_PAGE, _DAC_CFG_REGISTER,

lambda v: _set_bit(v, _CLAMP_SEL_OUTA0_BIT, True)

)

7. write_register_paged(_DAC_BUFFER_PAGE, _DACA0_BUFFER_REGISTER, code) --- used code for 1.5V

8. write_register_paged(_DAC_BUFFER_PAGE, _DACA1_BUFFER_REGISTER, code) --- used code for 0V

9. self._update_paged_register(

_GLOBAL_PAGE, _DRVEN_REGISTER,

lambda v: _set_bit(_set_bit(v, _DRVEN_DACA0_BIT, enabled), _DRVEN_DACA1_BIT, True)

)

10. update_paged_register(

_GLOBAL_PAGE, _DRVEN_SW_EN_REGISTER,

lambda v: _set_bit(v, _DRVEN_SW_EN_DACA0_BIT, True)

)

11. update_paged_register(

_DAC_CONFIG_PAGE, _DRVEN0_EN_REGISTER,

lambda v: _set_bit(v, _DRVEN0_EN_DACA0_BIT, False)

)

12. update_paged_register(

_DAC_CONFIG_PAGE, _DRVEN1_EN_REGISTER,

lambda v: _set_bit(v, _DRVEN1_EN_DACA0_BIT, False)

)

13. update_paged_register(

_DAC_CONFIG_PAGE, _FLEXIO_EN_REGISTER,

lambda v: _set_bit(v, _FLEXIO_EN_DACA0_BIT, False)

)

Test Loop:

14. write_register_paged(_DAC_BUFFER_PAGE, _DACA1_BUFFER_REGISTER, code) --- used code for 1.2V

loop 5x {

15. update_paged_register(

_GLOBAL_PAGE, _DRVEN_REGISTER,

lambda v: _set_bit(_set_bit(v, _DRVEN_DACA0_BIT, True), _DRVEN_DACA1_BIT, True)

)

-- pause --

16. write_register_paged(_GLOBAL_PAGE, _TRIGGER_REGISTER, (1 << _ADC_TRIG_BIT))

17. read_register_paged(_GLOBAL_PAGE, _GEN_STATUS_REGISTER) --- loop on this until the conversion is complete, max 5ms

18. read_register_paged(_GLOBAL_PAGE, _ADC_SENSE0_REGISTER)

19. update_paged_register(

_GLOBAL_PAGE, _DRVEN_REGISTER,

lambda v: _set_bit(_set_bit(v, _DRVEN_DACA0_BIT, False), _DRVEN_DACA1_BIT, True)

)

-- pause --

}

Spark!

Interpretation of above:

Initialization

1. Read: Page 0x00, Reg 0x40

2. Read: Page 0x00, Reg 0x41

3. Write: Page 0x03, Reg 0x42 --> 0b00000000

4. Write: Page 0x00, Reg 0x08 --> 0b00000011

5. Write: Page 0x00, Reg 0x12 --> 0b00000011

6. Write: Page 0x03, Reg 0x42 --> 0b00000001

7. Write: Page 0x04, Reg 0x40 --> 0b0000010011001101 (0x04cd, 1229 counts, 1.5V)

8. Write: Page 0x04, Reg 0x41 --> 0b0000000000000000 (0x000, 0 counts, 0V)

9. Write: Page 0x00, Reg 0x13 --> 0b00000011

10. Write: Page 0x00, Reg 0x12 --> 0b00000001

11. Write: Page 0x03, Reg 0x50 --> 0b00000000

12. Write: Page 0x03, Reg 0x51 --> 0b00000000

13. Write: Page 0x03, Reg 0x52 --> 0b00000001

Test Loop

14. Write: Page 0x04, Reg 0x41 --> 0b0000001111010111 (0x03d7, 983 counts, 1.2V)

loop 5x {

15. Write: Page 0x00, Reg 0x13 --> 0b00000011

-- pause --

16. Write: Page 0x00, Reg 0x12 --> 0b00000001

17. Read: Page 0x00, Reg 0x03 --- keep reading this on a loop until conversion is complete for a max of 5ms

18. Read: Page 0x00, Reg 0x18

19. Write: Page 0x00, Reg 0x10 --> 0b00000010

-- pause --

}

SPARK!

---------

Thanks for all your help,

Nathan

RE: AMC7908EVM: AMC7908EVM Sparked and blew up

Erin Bowrie — Wed, 06 May 2026 23:41:21 GMT

Hi Nathan,

Well, that's an unfortunate turn of events...

The USB causing the board to go hot is an interesting clue. The USB is set up to power VIO and VDD by default, so if the board feels hot with it plugged in that means VDD is likely busted and drawing extra current. Remove the J13 VDD jumper and apply power externally to the J5 banana jack. If it draws a high amount of current, that may be part of our culprit. If it doesn't, try VIO as well (I wouldn't expect VIO to break like this though). It looks like your VSS is also drawing high current, 300mA is very high.

It looks like the black marks on the die are close to the VCCB/A inputs. May be a trick of the light, but the VCCB pad looks different than the other pads. This may be more clues that VCC turning off is causing our issue here.

Can you give me a detailed list of register writings you're using before the board blows up? I'd like to try to recreate the experiment.

Thanks,
Erin

RE: AMC7908EVM: AMC7908EVM Sparked and blew up

Nathan Kidd — Wed, 06 May 2026 22:31:20 GMT

Erin,

1) Not sure how to test all of these, since I thought the jumpers automatically controlled the voltage output on these ports? On Vcca, 0A with 5V applied. On Vss, 0.3A with 0V applied (sinking into power supply somehow). The VIO and VDD had voltages on them.

2) There aren't, however the AMC has visible holes in the package. In addition, the AMC gets very hot when the USB cable is plugged in, even when nothing else is plugged in. It cools when the USB cable is disconnected

3) I had a communication loop going which was telling the AMC in software to turn on and off the gate voltage (I now realize it wasn't in DRVEN mode, it was being controlled by software). I believe it was working for a little while before crashing out.

Finally, the replacement kit you sent also burnt out... I disconnected the FGEN which was pulsing the DRVEN completely as I feared it was causing an issue, then ran my test again. During my testing, the power supply once again got turned off (possibly my program is doing this??? not exactly your problem but why is it off!!! UGH) and just during software gate "on-off-ing" it broke the same way after 5 pulses, with little holes in the same place.

Nathan

AFE7900: NCO Phase Accumulator Reset after Freq Change

arye nudelman — Tue, 24 Mar 2026 17:59:29 GMT

Part Number: AFE7900

Hi is there an option to reset the NCO phase accumulator after frequency hopping was done? (using the same NCO)

RE: AFE7900: NCO Phase Accumulator Reset after Freq Change

David Chaparro — Wed, 06 May 2026 16:29:24 GMT

Hi Arye,

Can you please share more information on what exactly you are trying to achieve by resetting the phase accumulator? With only a single device there should not be a need to reset the phase as all channels will be aligned and the AFE maintains the phase of each NCO when not in use.

Regards,

David Chaparro

RE: LMX2695SEPEVM: Is there a datasheet available for the LMX2624 & LMX2695-SEP

Noel Fung — Wed, 06 May 2026 16:24:06 GMT

Hi There,

SP (or SHP) and SEP devices have different radiation immunity level, the functionality and electrical performance are usually identical. LMX2595 is an industrial grade device.

LMX2695SEPEVM: Is there a datasheet available for the LMX2624 & LMX2695-SEP

ken mason — Wed, 06 May 2026 13:54:08 GMT

Part Number: LMX2695SEPEVM

In the 2026 TI Space Products Guide there is mention of the LMX2624-SP & LMX2695-SEP (page 16).

I can find the LMX2624-SP datasheet but not the LMX2695-SEP, what is the difference?

How does the LMX2695-SEP differ from the LMX2595, is there any radiation data on the LMX2595?

AFE7900: Unexpected behaviour of RX channel in system mode 3.

Noumeer Piracha — Fri, 27 Mar 2026 10:51:20 GMT

Part Number: AFE7900

Currently working on the AFE7900, where two receive channels are being used in system mode 3. Each channel uses two lanes with a sampling rate of 184.32 MHz. Channel 1 has an NCO set to 120 MHz, and Channel 2 has an NCO set to 415 MHz.

After receiving the data on two lanes, it is reconstructed in RTL, and a data plot at 368.64 MHz has been generated. One of the channels shows unexpected output, as illustrated. What could be the possible cause of this issue?

AFE Latte script is as follows:

setupParams.skipFpga 				= 1
sysParams							=	AFE.systemParams
#setupParams.fpgaRefClk 				= 122.88
setupParams.fpgaRefClk 				= 184.32	
#setupParams.fpgaRefClk 				= 256.00
AFE.systemStatus.loadTrims			= 1

sysParams.FRef                    	= 491.52
sysParams.FadcRx                  	= 2949.12
sysParams.FadcFb				  	= 2949.12
sysParams.Fdac                    	= 2949.12 * 3
#sysParams.FRef                    	= 512
#sysParams.FadcRx                  	= 3072
#sysParams.FadcFb				  	= 3072
#sysParams.Fdac                    	= 3072*3

sysParams.rxJesdTxScr   = [False, False, False, False]
sysParams.fbJesdTxScr   = [False, False]
sysParams.jesdRxScr     = [False, False, False, False]


sysParams.rxEnable		            =	[True,True,True,True]
sysParams.txEnable                  =   [True,True,False,False]
sysParams.fbEnable	            	=	[False,False]
sysParams.enableDacInterleavedMode	= False 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
#sysParams.jesdSystemMode			= [0,0]
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
#sysParams.LMFSHdRx                	=['48410', '48410', '48410', '48410']
sysParams.LMFSHdRx                	=['44210', '44210', '44210', '44210']
#sysParams.LMFSHdRx                	=['14810', '14810', '14810', '14810']
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["22210","22210"]
#sysParams.LMFSHdTx                	= ["24410","24410","24410","24410"]
# sysParams.LMFSHdTx                	= ["12410","12410","12410","12410"]
sysParams.LMFSHdTx                	= ["44210","44210","44210","44210"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
#sysParams.jesdTxLaneMux				= [0,1,4,5,2,3,6,7]	
# # sysParams.jesdTxLaneMux				= [4,5,2,3,0,1,6,7]
sysParams.jesdTxLaneMux				= [0,1,2,3,4,5,6,7]
# sysParams.jesdTxLaneMux				= [0,1,4,5,2,3,6,7]
#sysParams.jesdTxLaneMux					= [4,5,6,7,3,0,1,2]
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]


sysParams.jesdRxLaneMux				= [0,1,2,3,4,5,6,7]	
# sysParams.jesdRxLaneMux				= [2,3,4,5,0,1,6,7]
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]


# sysParams.dacDataMuxEn      =  0 #to enable datamux
# sysParams.txDataMux					= [2,3,0,1,4,5,6,7]
# sysParams.txDataMux					= [2,3,4,5,0,1,6,7]
# sysParams.txDataMux					= [6,7,4,5,2,3,0,1]
sysParams.jesdRxRbd					= [4, 4]
sysParams.jesdTxRbd					= [1, 1]
sysParams.fbDataMux                 = [0,1]
sysParams.rxJesdTxScr				= [False,False,False,False]
sysParams.fbJesdTxScr				= [False,False]
sysParams.jesdRxScr					= [False,False,False,False]

sysParams.rxJesdTxK					= [32,32,32,32]
sysParams.fbJesdTxK					= [32,32]
sysParams.jesdRxK					= [32,32,32,32]

#sysParams.ncoFreqMode 				= "1KHz"
sysParams.ncoFreqMode 				= "FCW"	
sysParams.txNco0					= 	[[170,170],		#Band0, Band1 for TxA for NCO0
										[418,418],        #Band0, Band1 for TxB for NCO0
										[400,400],        #Band0, Band1 for TxC for NCO0
										[400,400]]       #Band0, Band1 for TxD for NCO0


sysParams.rxNco0					= 	[[170,170],		#Band0, Band1 for RxA for NCO0
										[418,418],        #Band0, Band1 for RxB for NCO0
										[400,400],        #Band0, Band1 for RxC for NCO0#
										[400,400]]        #Band0, Band1 for RxD for NCO0
										
sysParams.fbNco0					= 	[150,150]		#FBA, FBC for NCO0


sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

# sysParams.ddcFactorRx             	= [24,24,24,24]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorRx             	= [8,8,8,8]			# DDC decimation factor for RX A, B, C and D
# sysParams.ddcFactorFb             	= [24,24]
sysParams.ddcFactorFb             	= [8,8]
sysParams.ducFactorTx             	= [24,24,24,24]
# sysParams.ducFactorTx             	= [48,48,48,48]
# sysParams.ducFactorTx             	= [36,36,36,36]
# sysParams.ducFactorTx             	= [72,72,72,72]

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.sysrefFreq				=	3.84
# lmkParams.sysrefFreq				=	1.92
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x21
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 0
sysParams.jesdCDLvdsSync			= 0
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'DAC_SYNC0',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'ADC_SYNC1',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD', 
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
# AFE.systemParams.papParams[0]['enable'] = True
# AFE.systemParams.papParams[1]['enable'] = True
# AFE.systemParams.papParams[2]['enable'] = True
# AFE.systemParams.papParams[3]['enable'] = True
		

## Initiates LMK04828 and AFE79xx Bring-up
setupParams.skipLmk	=	False

AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
## Initiates AFE79xx Bring-up
setupParams.skipLmk	=	True
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,0,15)
# AFE.JESD.ADCJESD[0].adcRampTestPattern(0,1,0) #RXA
# AFE.JESD.ADCJESD[0].adcRampTestPattern(1,1,0)	#RXB
# AFE.JESD.ADCJESD[0].adcRampTestPattern(2,1,0) #FBAB

# AFE.JESD.ADCJESD[1].adcRampTestPattern(0,1,0)	#RXC
# AFE.JESD.ADCJESD[1].adcRampTestPattern(1,1,0)	#RXD
# AFE.JESD.ADCJESD[1].adcRampTestPattern(2,1,0)	#FBCD


# AFE.JESD.DACJESD[0].dacJesdConstantTestPatternValue(1,0,0,32767,0)
# AFE.JESD.DACJESD[0].dacJesdConstantTestPatternValue(1,1,0,32767,0)
# 
# AFE.JESD.DACJESD[1].dacJesdConstantTestPatternValue(1,0,0,32767,0)
# AFE.JESD.DACJESD[1].dacJesdConstantTestPatternValue(1,1,0,32767,0)

RE: AFE7900: Unexpected behaviour of RX channel in system mode 3.

David Chaparro — Wed, 06 May 2026 15:39:08 GMT

Hi Noumeer,

I believe the reason you are seeing this is because of a combination of your bandwidth/interface rate and NCO settings. With an interface rate of 368.64Msps and NCO of 120MHz, you are capturing data from 120+/- 184.32MHz. This means that you are capturing the DC spur which may be causing the issue you are seeing.

I recommend updating the NCO such that the DC spur is not in band and this should go away.

Regards,

David Chaparro