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Clock Configuration (0x05) for an external clock

Minkyun Noh
Prodigy 170 points

Hello,

I am trying to stream out the frequency count data (0x23 through 0x25) using an external clock (5MHz).  

Thanks to Vitaliy's help, I was able to read out the data by configuring Clock Configuration (0x05) as CLK_SEL =0 and CLK_PD=0.

But this conflicts with what the datasheet (Table 9 in Ver. C SNOSCX2C) says:

CLK_PD
0: Crystal drive enabled.
1: Crystal drive is disabled. Use this setting to reduce power consumption with a crystal input when device is in Standby mode. Use this setting for clock input.

Could TI people explain if the datasheet is wrong?

Also, I can get the frequency count data only by reading from 0x21 through 0x25. If I try to read from 0x23 through 0x25, it does not work. Is there a way to just read out the frequency count data, so that I can save some time for higher sampling rate?

Best regards,

Minkyun

  • 0
    TI__Genius 13650 points
    Hello Minkyun,

    > But this conflicts with what the datasheet (Table 9 in Ver. C SNOSCX2C) says:
    I apologize, the datasheet is indeed wrong. The register map description should read:
    CLK_PD
    0: Crystal drive enabled. *Use this setting for clock input.*
    1: Crystal drive is disabled. Use this setting to reduce power consumption with a crystal input when device is in Standby mode.

    > Also, I can get the frequency count data only by reading from 0x21 through 0x25. If I try to read from 0x23 through 0x25, it does not work. Is there a way to just read out the frequency count data, so that I can save some time for higher sampling rate?
    Register 0x21 is the trigger register for all data (RP and L). It must be read for the data to update.
    You can choose whether or not you wish to read register 0x22, but skipping it may not necessarily faster if you are using the extended SPI protocol with auto-increment.