Hello
In design of a cascaded system with 2 AWR1243 chips, i want to ignore number of pins like that:
QSPI pins, JTAC pins excep TDO, GPIO pins, RES pins, UART pins, Analogtest1 to 4 ANAMUX and VSENSE, ,and OSC_CLKOUT in slave.
1- Do these pins pulled up or down?
2-In design, some of pins like SYNC_OUT must be poor pulled up/down. If voltage of IO is 1.8v, is the 10K resistance appropirate for pulling up/down?
thanks for your attention
