tmp100: TMP100 - Unclear I2C Timing Diagrams

Carlos Silva85

Part Number: TMP100

For the TMP100, I need to know the timing for it to send out data relative to the clock edge, I.e. time from I2C clock driven low (usually from processor) to data being valid on SDA line.

I refer to the figure below, which can be found on page 12 of the data sheet, which doesn't seem to make this information very clear.

over 6 years ago

0 Ren Schackmann over 6 years ago

TI__Mastermind 35895 points

Hi Carlos,

Data Hold Time (HDDAT) is the time that data logic level must be retained after clock fall. Data Setup Time (SUDAT) is the time that data logic level must be valid prior to rising clock edge. The data logic level can change at any time between the buffer zone for these two parameters, and in fact the window of opportunity (so to speak) will be quite large dependent on your clock speed.

Thanks,
Ren

0 Bob Bacon over 6 years ago in reply to Ren Schackmann

TI__Genius 10815 points

Hello Ren
From my understanding of what you explained, this sounds like timing for Slave Receive mode.

What we want is timing in SLave Transmit mode.

How long is it from SCL going low to the data being valid ?

Thanks
Bob

0 Ren Schackmann over 6 years ago in reply to Bob Bacon

TI__Mastermind 35895 points

Hi Bob,

You're asking about the parameter known as tVD;DAT in the NXP I2C Spec. This parameter sometimes appears as HDDAT MAX in our datasheets. In the literature, this parameter is calculated based on the expected system frequency, and doesn't reflect actual device propagation delay. In the case of TMP100, the actual propagation delay (in both FS and HS modes) is the number shown as HDDAT MAX for HS Mode, 170ns.

Thanks,
Ren

Sensors

Sensors forum

tmp100: TMP100 - Unclear I2C Timing Diagrams