hello all,
I have got another question about AFE5809, regarding to the minimal LVDS output lanes that I should connect to the FPGA.
An AFE5809 has 8 channels and 8 LVDS output lanes, from tabel 13 of the datasheet, we can use only 2 LVDS output lanes for each demodulator output, that's 4 for each AFE.
while the LVDS_OUTPUT_RATE_2X register is discripted as:
The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges
of the LVDS bit clock, DCLK. The output rate is set by default to 1× (LVDS_OUTPUT_RATE_2X = 0), where
each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one
LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs will
output zero. To avoid consumption from those outputs, no termination should be connected to them. The
distribution on the used output pairs is done in the following way:
• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first.
Is there some way that I could make usage of these two features, so that I can only use 2 LVDS output lanes (NO.3 and NO.5) to output the whole 8 demudulated digital signals?
thanks a lot!
