Other Parts Discussed in Thread: LDC1041, LDC1001
Hello,
I am currently working with the LDC1101 and am getting nice data out of it. I would like to speed things up and switch to DMA + interrupt driven polling on my ST micro, and had some questions while reading the datasheet.
Figure 55 seems to imply that CS needs to go low in order for SDO to latch low as per a data ready signal (this makes sense considering it could be a shared bus, although mine is not).
If I am setting up an interrupt to do this, how can I check for it to go low without constantly checking by switching the CS line low? This feels like it defeats the purpose of the interrupt from a speed perspective, but I can appreciate that it prevents us from constantly polling the sensor with an entire read function.
Am I missing something here? Considering I don't have a shared bus I suppose I could leave CS low when not polling and then let the interrupt trigger naturally. If I do this I suppose I would need to disable the interrupt during my SPI read to prevent it from triggering on the actual SDO rising/falling edges?
I am making a rotary encoder, and am aiming for SPS in the 50kHz range.
Thanks for your help,
Dave
