AWR1243: VCO and Ramp generation architecture

The information available is provided in the datasheet.

Is the customer interested about any specific features?

Thank  you

Cesar

Yeah, It would be great what kind of VCO is used ? what kind of PLL is used ?

Hi,

I will assign this to HW team

thank you
Cesar

Hello Maynard,

The high level bock diagram is provided in the datasheet. Basically we have 40Mhz reference clock going a clean up PLL to generate a 1.4Ghz clock for the RF PLL, which generates the 20Ghz LO. This is multiplied by 4 to get to the 80Ghz frequency..

Regards,
Vivek

Hi Vivek, 

Customer want to know the architecture of the VCO used? (LC, Colpitts, Cross Coupled). Similarly the architecture of the PLL used.

Regards,
Maynard

Hello Maynard,

We cannot share our internal design details. The specifications of the  clock (like phase noise) are mentioned in the datasheet.

Regards,

Vivek

Hi Vivek,

Thank you for confirming.

Regards,
Maynard