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TDC7200: SPI mode(s) to be used

Part Number: TDC7200
Other Parts Discussed in Thread: TDC7201

Dear TI team,

the datasheets for the TDC7200 (Fig. 1, page 8) and TDC7201 (Fig. 1, page 7) postulates:
  DIN: SCLK rising edge
  DOUT: SCLK falling edge
In consequence, the SPI-mode of a MCU SPI-block would have to be changed during a single register read transfer after sending the address
The 7200 diagram shows a real shift of DIN and DOUT in Fig. 1, but the diagram of Fig.21, page 22 does not!
The 7201 diagram does not show a shift.

What is the truth ? Which SPI mode(s) can we use?

Kind Regards



  • Hello Martin,

    Thank you for your question. It seems to me that Figure 1 of the TDC7200 does not properly portray what occurs in a SPI transaction. Please refer to Figure 21 of the TDC7200 data sheet as that one seems to correctly correlate how the device behaves. To verify I took a screenshot of a register read on the logic analyzer, it can be seen below:

    I hope this answers your question.



  • Dear Isaac,

    thanks for your answer!
    Now we are confident to drive the TDC7200/7201 with CPOL:=0 (Clock idle low) and CPHA:=0 (Sample @ rising edge)
    what is similar to SPI mode 0