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AWR1243: Enable the debug Output via USB cable or Serial port or JTAG

Part Number: AWR1243

Hello All,

Connecting the AWR1243 to processor board. 

Now AWR1243 is not giving any interrupt to processor board.

To check that what SPI command, it is receiving or What is happening inside the AWR1243 board,

need to enable the debug output on it. 

Do we have any provisions to get the Debug output via serial cable or USB cable or JTAG cable?

We are using AWR1243 Booster EVM. From Host, SPI commands may be wrong due to wrong timing parameters.

-Thanks.

  • Hi,

    We recommend that you try to run the mmwave link example on the host. This example includes all the steps required to communicate with the AWR1243

    Thank you

    Cesar

  • Hi Balaji,

    If Host is not able to send the SPI command in the format or in specification what AWR understands then it will totally ignore all those data. Even it won't proint anything in log.

    MSS and BSS dumps the debug logs over UART lines but I don't think that is required here. As it is some basic SPI setting mismatch at Host end.

    https://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/856058/faq-queries-related-to-mmwave-dfp (Q3 and Q4)

    AWR device raises HostIRQ as soon as it is powered up, Host needs to make sure that it sets the SOP setting first and reset the AWR device. And it should follow the timing requirement as mentioned in the datasheet.

    https://www.ti.com/lit/ds/symlink/awr1243.pdf (section 5.9.1)

    And after this hardle is over you need to check SPI connection as well (above datasheet: section 5.9.4.2)

    Regards,

    Jitendra

  • Hello Jitendra,

    Thanks for the reply.

    we are trying as follows:

    1. SOP setting - We are not doing this in software. Before power on, SOP mode sets to functional mode using jumpers.

    2. Reset the AWR - We are not doing this in software by nReset signal. In AWR1243 board,

    using the Reset switch for this.

    3. In Host processor, header, probed the spi pins. They looks good, i.e. We sent some data

    and see this in protocol Analyzer. Signals CS, Clk, Mosi, Miso.

    But when we connect the AWR1243 board with host processor using cable (10cm length), then SPI chip select signal is always high and see some small noise in this. So We removed the Pull up resistor in AWR1243 board. Still chip select signal is not working properly. We checked the chip select signals by sending some data from Host and probed using Protocol Analyzer.

    In Host processor, we sets the chip select signal to pull up mode.

    Please provide your inputs.

    -Thanks.

  • Hello Jitendra,

    Thanks for the reply.

    we are trying as follows:

    1. SOP setting - We are not doing this in software. Before power on, SOP mode sets to functional mode using jumpers.

    2. Reset the AWR - We are not doing this in software by nReset signal. In AWR1243 board, using the Reset switch for this.

    3. In Host processor, header, probed the spi pins. They looks good, i.e. We sent some data and see this in protocol Analyzer. Signals CS, Clk, Mosi, Miso.

    But when we connect the AWR1243 board with host processor using cable (10cm length), then SPI chip select signal is always high and see some small noise in this.

    So We removed the Pull up resistor in AWR1243 board. Then chip select signal is going as low and see the small signal changes in between the word transfer. This causes SPI transfer as error. We checked the chip select signals by sending some data from Host and probed using Protocol Analyzer.

    Connection is: Host processor <-> cables <-> Awr1243

    Here, cables are connected in protocol analyzer too.

    Please refer the attached image in this. 

    In Host processor, we sets the chip select signal to pull up mode.

    Please provide your inputs.

    -Thanks.

  • Hi,

    I would recommend you to first try with very short cable connection b/w Host processor and AWR device to confirm if  SPI setting and device connections are fine.

    Regards,

    Jitendra

  • Hello Balaji

    Is the "SPI ENABLE" signal in the above plot the CS signal? It looks like there is "glitch" on the CS signal inbetween the transaction which should not be present. It should remain low throughout the transaction and should go high only once the command is complete. In the snapshot you have shared the CS is going high inbetween for a short duration. This needs to be fixed in the host processor.

    Regards,
    Vivek