Dear all
I am using MSP430FR2355, I want to get ADC data from 3 different channel for example A3,A6,A7.
I could get ADC data separately from each channels, using change ADCINCH_XX in sample codes for each channels. I read reference (Ref User Guide (SLAU445I) Sec 21.2.7.2) and another question in support chat, I know that should use timer for it but I don’t know how to use it.
I have question:
- I want to get data from different channel one after other ( for example first A6, then A7 and finally A3).could you please let me know how to do it in my attach code?
- Also is it possible to get data from 3 different channel at the same time? If yes, could you please help me for it?
I look forward for your replay.
Best Regards
Hadi // ADC Configuration
ADCCTL0 |= ADCSHT_2; // 16 ADCCLK cycles
ADCCTL0 |= ADCON; // ADC ON
ADCCTL1 |= ADCSHP; // ample-and-hold pulse-mode select ==>> ADCCLK = MODOSC; sampling timer
ADCCTL2 &= ~ADCRES; // clear ADCRES in ADCCTL
ADCCTL2 |= ADCRES_2; // 12-bit conversion results
ADCCTL1 |= ADCCONSEQ_0;
ADCMCTL0 |= ADCINCH_3; // ADC input Channel Port 1.3
// ADCMCTL0 |= ADCINCH_6; // ADC input Channel Port 1.6
// ADCMCTL0 |= ADCINCH_7; // ADC input Channel Port 1.7
ADCIE |= ADCIE0; // Enable the Interrupt request for a completed ADC_B conversion
ADCCTL0 |= ADCENC; // Enable conversions
ADCCTL0 |= ADCSC; // Start conversion
ADCCTL0 |= ADCMSC;
__bis_SR_register(LPM0_bits | GIE); // LPM0, ADC_ISR will force exit
__no_operation();
}
}
// ADC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISRAI1(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISRAI1 (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
{
case ADCIV_NONE:
break;
case ADCIV_ADCOVIFG:
break;
case ADCIV_ADCTOVIFG:
break;
case ADCIV_ADCHIIFG:
break;
case ADCIV_ADCLOIFG:
break;
case ADCIV_ADCINIFG:
break;
case ADCIV_ADCIFG:
ADC_Result[i] = ADCMEM0;
__delay_cycles(400);
__bic_SR_register_on_exit(LPM0_bits); // Clear CPUOFF bit from LPM0
break;
default:
break;
}
}