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AWR1843AOP: What's the impact on the PCB Surface Wave on AWR1843AOP EVM?

Part Number: AWR1843AOP
Other Parts Discussed in Thread: AWR1843, ,

Hi team,

In AWR1843 errata, "PACKAGE#02A Surface Wave Artifact from PCB" mention that we need to Keep the Edge of PCB close to the edge of the AoP device in the E-plane to minimize the
surface wave ripples.

But the AWR1843AOP EVM didnot follow this rules. So what's the result on AWR1843AOP EVM? Do we have any new workaround to avoid this issue?



  • Hello Wesley,

    We did some testing with the AWR1843AOPEVM and saw that there was only a small impact to the antenna gain pattern with the section of the PCB around the device. The gain pattern can with the current PCB design be found in the user's guide. 

    If you keep a similar form factor and component placement to the EVM, you can maintain similar performance to the EVM. If you do need to keep a small section of PCB around the device, make sure to avoid placing any components in that area, as having components in the area can further degrade the performance. I would recommend to add the cutout as in the errata workaround if possible. If it is not possible to have the cutout, try to keep the design as close to the EVM as possible.  



  • Hi Adrian,

    Thanks for your detail reply. I want to understand what's the meaning of "If it is not possible to have the cutout, try to keep the design as close to the EVM as possible.

    Is it means try the best to keep the PCB cut close to the silicon edge?