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TMP75: Question about I2C spec t(HDDAT)

Part Number: TMP75

Hello,

My customer is using TMP75

Their host is communicating with TMP75 via I2C interface.

They are using Fast-mode, fSCL=100KHz and tLOW(LOW period of the SCL clock)=5us

They are measuring I2C timing at their test bench and confirmed t(HDDAT) is 1475ns, larger than 900ns specified as maximum t(HDDAT) in the datasheet. But, the host can properly communicate with TMP75 somehow.

The maximum t(HDDAT) spec, 900ns, is just cut & copy from NEP spec?
And TMP75 can communicate with host even if t(HDDAT) > 900ns?

Best regards,

K.Hirano

  • Hello,

    Yes, most of the TMP75 I2C timing specification is based on the I2C standard, although many of the parameters will not affect our devices operation.  The spec is written around a specific frequency and our device does not predict the frequency as it must be functional across a wide range of frequencies.  

    Edge to edge timing is one spec that could affect our device.  The data must be setup and steady prior to a rising clock edge or we may sample the wrong value at the clock edge.  If the data is not held after the clock edge falls, we may have a corrupted interpretation of SDA state of the previous clock.  We have a max frequency spec for fast mode(400kHz) and we do not change our behavior over the entire frequency range in fast mode.  You will notice that the spec is different for the high speed mode.    

    While the device may communicate properly in your testing, we cannot guarantee any behavior that is outside of the device datasheet specifications.