TMP112: Register access exception

Hello Andy,

We specify a typical and max, but not minimum for the timeout spec.  Have they seen this behavior on multiple devices? 

As SCL is controlled by the master device, can they have their microcontroller release the SCL line during this period to see if they have the same results?   

Also, what is the clock frequency?

Hi LaCost,

Yes, customer test different boards, and see the same behavior;

The reason why SCL is continuously pulled down is that the program allows the interrupt clock to be switched to do other things during this time, and then switch back after completion; the program is a third-party module, so the customer cannot modify it directly. The essential problem is that The program has bugs;

But customer wants to determine if this triggers a timeout so that they and the end client can assess the risk;
Note two issues:
1. The SCL pull-down time of different boards will vary by 1~2ms, between 25~27ms. So we have relevant test data to clarify the shortest SCL pull-down time triggered by timeout?
2. When SCL is pulled low and then pulled high, it will return two bytes, and an error occurs from the very beginning, such as the waveform I sent at the beginning; sometimes after trying to return the first byte (device address), An error occurs in a certain bit of the second byte. Does this conform to the timeout rule? At the same time, SCL is pulled low to trigger the timeout phenomenon.

Please help me check, thanks LaCost.

Best regards,

Andy Liu

Hi LaCost,

The I2C clock is 100kHz.

Hi LaCost,

My customer also test our INA3221 for comparing;

And I find INA3221 Spec said timeout 28~35ms; and customer pull down SCL about 199ms, and INA3221 also can return the right value, like below, they read INA3221(0x41) 0x00 register, and then SCL pull down 199ms, then release and return value 0x71 0x27 which is the right value.

Is the timeout mechanism of TMP112 and INA3221 the same? Why are the results different, please help to answer thank you.

Andy,

The TMP112 does not have control of the SCL line, so this must be controlled by the master.  As register 0x03 is a limit register, is it possible that they have set this to 0xFF and the reading is correct?

Hi LaCost,

Yes, the SCL line is controlled by the master. I will confirm with the customer the information of the 0x03 register.
But how to understand our timeout information? I can't find relevant information in Spec, can you help me find the timeout protection information, thank you.

Hi LaCost,

Customer set 0x03 register 0x50 0x00, 80°C, is not 0xFF, please help me check why we return 0xFF, thanks.

Hi LaCost,

Customer use the default 0x03 Thigh register, is 80°C 0x50 0x00;

And LaCost, this does not seem to be related to the problem measured by the customer. When they use the TMP112 Master to pull the SCL low for 27ms, the triggered timeout phenomenon is different from that when the INA3221 is used to trigger the timeout;
This makes customers wonder about our timeout action mechanism, and I did not find any instructions related to timeout. Please help to answer. Thank you.