AWR6843AOP: Generic questions with AWR6843AOP

Hello,

   Please find the answers for the below questions.

1. Datasheet says VPP pin is “Voltage supply for fuse chain”. What exactly is EFUSE programming? They need additional 1.7V to supply this pin, and they want to know what function this pin is for.

[Chethan]  Device family comes with the general and secure variant: Secure device provides the infrastructure features such as secure boot (using a signed image) and locking out debug access besides other features. TI provides the MMWAVE-SECDEV package which is used with HS(High Secure) devices. Access to this package is provided only on a request basis. Please get in touch with your local TI sales office to learn more.

The following page provides an overview of security in context of TI devices.

https://www.ti.com/technologies/security/overview.html

For secure devices will have one time EFUSE programming, for blowing the fuses we would use VPP pin with 1.7V supply. 

2. If the customer will not use LVDS, could related power pins be left floating as well ? (including VPP, VIN_18CLK VIOIN_18DIFF)

[Chethan] If the LVDS pins are not used then it could left floating, and VPP is for the blowing the EFUSES if the security feature is general then VPP pin could be left floating. 

However other pins like VIN_18CLK or VIOIN_18DIFF cannot be left floating, they are used for other purpose as well.  Hence they need to be connected as in the reference design. 

3. Is OSC_CLKOUT an output pin for clock synchronization with external host?

[Chethan] This pin is meant for clock synchronization with multi-chip cascading configuration, currently this feature is not supported in the current version. Hence this pin could be left floated. 

4, If the customer is not willing to use external MCU or processor, can MCU_CLKOUT pin be left floating?

[Chethan] Yes.

5. I've been informed that PMIC_CLKOUT is for clock dithering. What is clock dithering? And can this pin connected to PMIC(LP8752J)'s CLKIN pin?

[Chethan] This pin is used as one of the boot mode pin (SOP ) , Hence this need to be connected as for pull up or pull down depending upon the boot mode desired. You could refer to reference EVM for pullup/pull down. LP8752J has it's own clock dithering scheme, Hence this pin need not be connected to LP8752J's CLKIN pin.

6. According to Data sheet and EVB circuit, NERROR_IN and NERROR_OUT pins are pull up. Should NERROR_OUT be connected to PMIC'S reset pin for resetting AWR6843 since it acts as active low during internal error?

[Chethan] NERROR_IN & NERROR_OUT are used for the asserting the fault in the system. Assertion of the NERROR could happen for various reasons, Device records reason for the NERROR assertion in the ESM (Error status monitoring Module registers) by reading the ESM registers next actions could be taken. 

And NERROR_IN receives external error signal, can this also be used to receive Interrupt signals from other ICs? (PMIC nINT signal, CAN IC(TJA1043)'s error signal )

[Chethan] NERROR_IN receiving the external error signal, NERROR pin is open drain type of I/O not GPIO, Hence it cannot be connected to other I/Os where NERROR handling mechanism is not present, Current generation of PMIC doesn't support NERROR signals, There are few external processors and upcoming PMICs are capable of handling NERROR signals where this could be connected.  

7. During sleep state like Low Power mode, which pin can AWR6843 receive external interrupt signal?  Which pin of AWR6843 should they select to receive wake-up external interrupt input?

[Chethan] Low power mode is enabled through the firmware not by external interrupt signals, For more information on the low power and mode transitions you could refer to below link

https://dev.ti.com/tirex/explore/node?node=ALNwx9A2x.o5T7wR85tZlQ__VLyFKFf__LATEST

Thanks and regards,

CHETHAN KUMAR Y.B.