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TDC7200: Overflow in multi-cycle averaging

Nikolay Panev
Prodigy 10 points
Part Number: TDC7200

Hello,

I'm designing a device to measure time intervals in the range 10-30us using TDC7200 in Mode 2. I'd like to use also multi-cycle averaging to average 16 measurement cycles. The datasheet does not clearly say what would happen if Coarse or Clock Counters overflow occurs. So here are my questions:

1. Is the entire multi-cycle averaging process terminated? Or is it just the single current cycle measurement stopped?
2. Do I need to initiate a new multi-cycle averaging measurement process by setting the START_MEAS bit in CONFIG1 register?

Thanks!
Nikolay

  • 0
    TI__Mastermind 19610 points

    Hey Nioklay,

    Thanks for posting to the PS forum! We will review your question and submit a response tomorrow. Thanks for your patience!

    Best,

    Isaac

  • 0 in reply to Isaac Lara
    TI__Mastermind 19610 points

    Hello Nikolay,

    Sorry for the delay, I should be able to check this in the lab today, I will get back to you by the end of the day. Thanks!

    Best,

    Isaac

  • 0 in reply to Isaac Lara
    TI__Mastermind 19610 points

    Hello Nikolay,

    Thank you for your patience. 

    1. Is the entire multi-cycle averaging process terminated? Or is it just the single current cycle measurement stopped?

    If a STOP signal is not received then the clock will overflow, the INT_STATUS (0x02) will reflect that an overflow has occurred. If the device receives another START pulse with the correct amount of STOP signals the device will status register will indicate that the measurement has been completed. So MEAS_COMPLETE_FLAG bit will be asserted as well as NEW_MEAS_INT indicating that a new measurement has been completed. 

    2. Do I need to initiate a new multi-cycle averaging measurement process by setting the START_MEAS bit in CONFIG1 register?

    In order to start a new multi-cycle measurement you will need to set the START_MEAS bit in register CONFIG1 (0x00). You should assume that the calculated average values stored in the TIMEn and CLOCK_COUNTn registers are incorrect and begin the new measurement.

    Please let me know if you have any additional questions!

    Best,

    Isaac

  • 0 in reply to Isaac Lara
    Prodigy 10 points

    Hi Isaac,

    Thank you for your answers!

    As I understand, if an overflow occurs (STOP signal is not received) then the current measurement is terminated but the multi-cycle averaging process continues and a new START signal will trigger the next measurement in the cycle. Am I correct? I understand that the average values in TIMEn and CLOCK_COUNTn will be inaccurate because of the overflow.

    What would happen if the last measurement of the 16 multi-cycle averaging overflows? Will INTB pin go low to indicate the cycle is complete and results can be read?

    Regards,
    Nikolay

  • 0 in reply to Nikolay Panev
    TI__Mastermind 19610 points

    Hello Nikolay,

    Yes you understood the behavior correctly. I did not confirm INTB behavior, but I believe INTB will not pull low since the measurement was not completed correctly. Allow me to test this tomorrow and I will get back to you once I have confirmed the behavior.

    Best,

    Isaac

  • 0 in reply to Isaac Lara
    Prodigy 10 points

    Hi Isaac,

    Thank you very much! Will you please make your tests using the following setup of the INT_MASK register:

    - NEW_MEAS_MASK - always set to 1.
    - CLOCK_CNTR_OVF_MASK - either set to 0 or to 1.

    For our application it's vital to know if INTB pin will go low in any of the above setups when using multi-cycle averaging and an overflow occurs.

    Thanks!
    Nikolay

  • 0 in reply to Nikolay Panev
    TI__Mastermind 19610 points

    Hello Nikolay,

    I confirmed INTB performance during multi-cycle operation. Every time a measurement is completed INTB will pull low and it will also pull low when a the counter overflows (when a STOP signal is not received).

    In your firmware once INTB is pulled low you can read the INT_STATUS register (0x02) if any of the counter overflow bits are enabled then it is safe to assume the values in the TIMEn and CLOCK_COUNTn registers are invalid. The test was done using all interrupts enabled (INT_MASK 0x03 = 0x07).

    I hope this helps and feel free to let me know if you have any additional questions!

    Best,

    Isaac

  • 0 in reply to Isaac Lara
    Prodigy 10 points

    Thank you very much!