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FDC2214: Interrupt management - data ready (timing and functionality)

Part Number: FDC2214

Hello!

I have a question regarding the use of interrupt for signaling when the data is ready.

I have managed to configure the chip FDC2214 in such way that I can use interrupt signaling with another master MCU. However I have noticed that in order to get see the interrupt repeat I must continously read the STATUS register of the device. When I read the status register the interrupt pin goes high again and when the data is ready the pin goes low. As I am developing an extremely time precise application I would like to clarify some of my questions. I would like to read my data with as much as possible the same frequency.

Could you confirm/explain next questions:

  1. The pin INTB is HIGH when new data is not ready in DATA_LSB_CHx and DATA_MSB_CHx registers?
  2. The pin INTB is LOW when new data is ready in registers?
  3. Pin INTB is not a type of interrupt pin that generates a short duration pulse when new data is ready?
  4. When pin INTB goes LOW new data can be read from register. In such way a falling edge signalises the new data?
  5. If I do not read status register the data in DATA_LSB_CHx and DATA_MSB_CHx registers will not be updated until i read the status register?

These are the questions that I was hoping you could answer. As I didnt find the data in datasheet I would ask for more detailed description of implemented interrupt funcionality.

Best regards,

Vasja Pirc

  • Hello Vasja, 

    1. Yes. INTB is high by default. 
    2. Yes. When new data is ready, INTB will go low. 
      1. INTB can be configured for different triggers so make sure the STATUS_CONFIG, ERROR_CONFIG, and CONFIG registers are set accordingly to how you want to use the pin. 
    3. INTB is latching so after it goes low, it will stay that way until one of 5 events occur: 
    4. Yes. A falling edge does correlate to new data when INTB is reporting the Data Ready status. 
    5. Yes. Reading the STATUS register signals the device to update the DATA registers so that the registers can't be changed by the next conversion while the registers are still being read. 

    Best Regards, 

    Justin Beigel