with reference to "">www.ti.com/.../awr2243.pdf
The text on TI page.no 29 states "delay of at least two SPI clocks between CS going low and start of SPI" and
not provided a similar statement for the last SPI clock to CS going high.
In TDA I captioned thus "After CSn=0 then SCLK starts after 145ns, and CSn=1 is 145ns after last SCLK=0"
let me know how much delay is required with external host, there is more delay(22us) in CS to SCLK for every spi write.
Praveen Kumar K