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AWR2243: "How to reduce the SPI SCLK to CSn delay in AWR2243 dfp SPI write"

Part Number: AWR2243


with reference to "">
The text on TI 29 states "delay of at least two SPI clocks between CS going low and start of SPI" and

not provided a similar statement for the last SPI clock to CS going high.

In TDA I captioned thus "After CSn=0 then SCLK starts after 145ns, and CSn=1 is 145ns after last SCLK=0" 

let me know how much delay is required with external host, there is more delay(22us) in CS to SCLK for every spi write.


Praveen Kumar K

  • Hi,

    Please let us know if you are using a TI board or custom board.

    For AWR2243 you should use the information provided in the AWR2243 datasheet.

    thank you


  • Hi Cesar,

    We are trying to use a custom board with a different host processor. We are using the Linux based DFP here. We see a larger delay in the CS to SCLK value of SPI lines when using DFP-based SPI writes. The delay is much smaller in TDA.

    We would like to know the minimum delay required for proper DFP communication and how to reduce it from our current 22us.

    We are using AWR2243 and referring to the same document.

    Thanks in advance.

    Santhana Raj

  • Hi,

    The information regarding SPI communication requirements are documented in the AWR2243 datasheet. This is silicon requirement.

    If there are delays in the SPI communication you would need to check the Host Linux Driver

    thank you