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TMP112: I2C standard mode timing requirements

Terry Hu
Intellectual 1250 points
Part Number: TMP112

Hi Team,

In TMP112 datasheet, it only has FAST MODE and HIGH-SPEED MODE timing requirements(no standard mode timing requirements).

As I know,  I2C runs as standard mode while clock frequency ≤100KHz. (Please correct me if I am wrong.)

Below is I2C standard-mode timing requirements of other TI parts I have read before.

Could you kindly confirm whether TMP112 is the same?

Thanks and regards.

 

Terry

  • 0
    TI__Guru* 91086 points

    Dear Terry - 

    Thanks for the post. The TMP112 does support standard mode I2C speeds and this is documented on page 7 in the Timing Requirements table, where you can see the clock frequency range is listed as 1kHz to 400kHz. 

  • 0 in reply to Josh Wyatt
    TI__Intellectual 1250 points

    Hi Josh,

    Thanks for your reply.

    My customer use TMP112 with standard mode I2C. 

    In TMP112 datasheet, t(HDDAT) spec is 100~900ns(Fast mode). They tested the I2C timing and found t(HDDAT)>900ns.So the result is fail.

    However, they did some investigation and found generally, I2C standard mode spec is different from TMP112 datasheet (Fast mode).

    For example, t(HDDAT) spec of standard mode should be <3450ns(not <900ns).

    Therefore, they doubt TMP112 I2C timing spec is not compliant to I2C standard and request us to check the TMP112 I2C timing spec.

    Could you kindly help to check again? Thanks!

    Terry

  • +1 in reply to Terry Hu
    TI__Guru* 91086 points

    Terry - 

    In the most recent version of the I2C spec (v7), notes 2 and 3 apply (they used to be notes 3 and 4 of the relevant table) - see page 44 of UM10204_I2C_Specification_v7_0. 

    [2] Ensure SCL drops below 0.3VDD on falling edge before SDA crosses into the indeterminate range of 0.3 VDD to 0.7 VDD.
    NOTE: For controllers that cannot observe the SCL falling edge then independent measurement of the time for the SCL transition from static high (VDD) to
    0.3 VDD should be used to insert a delay of the SDA transition with respect to SCL.
    [3] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK by a
    transition time.

    What frequency did they test at? Which controller did they use? This truly is not an issue that is real, that we have seen or have seen be an issue when measured correctly and using any of the I2C engines in MCUs and MPUs produced since this device was released. If they are operating at 100kHz or less, then hold time should be no more than 3.45uSec and up to 400kHz, 900nSec. 

  • 0 in reply to Josh Wyatt
    TI__Intellectual 1250 points

    Hi Josh

    Thanks for your supplement.

  • 0 in reply to Terry Hu
    TI__Guru* 91086 points

    you are welcome!