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TMP126: SCLK logic when /CS high

Koji Ikeda
Expert 6205 points
Part Number: TMP126

Hello support team,

My customer ask SCLK logic treatment when /CS high. could you support? Fig 8.5.2 looks like to show SCLK low, while Fig 7.7 looks like to show high, this makes customer confused.

Thanks,

Koji Ikeda

  • 0
    TI__Guru* 91206 points

    Dear Koji - 

    Figure 8-9 in section 8.5.2 is representing sending the optional CRC at the end. In other words ==> If the CRC is sent from the host controller to the TMP126, then the chip select line has to remain low for the CRC to be clocked into the TMP126. 

  • 0 in reply to Josh Wyatt
    TI__Expert 6205 points

    Josh-san,

    Thank you for your support. But, I'm not clear what you comment. If CS pin high, how they should set SCLK pin? Keep High? Low?

    Thanks,

    Koji Ikeda

  • 0 in reply to Koji Ikeda
    TI__Guru* 91206 points

    Koji - 

    In a SPI application, individual chip select lines are used to address the individual devices on a bus (as opposed to a protocol like I2C, where an address byte is sent).

    When the chip select line is set to low (in an active low chip select scenario like this one) for an individual device, bytes may be clocked in/out and the other devices on that bus will ignore the activity (data and clock) because their chip select lines are high. 

    This means that once a chip select line is brought high after communication is completed, the clock line could be in any state - in this case, after communication is complete, it (the clock line) would be low, but if there are other devices on the bus, it could be used to clock data from those devices and TMP126 will ignore that. 

  • 0 in reply to Josh Wyatt
    TI__Expert 6205 points

    Josh-san,

    Thank you for your support. Please let me confirm, in my understanding, SPI has CPOL and CPHA. Which mode TMP126 support? I assume that the clock logic during CS high would be up to the mode.

    Thanks,

    Koji Ikeda

  • +1 in reply to Koji Ikeda
    TI__Guru* 91206 points

    Koji -

    I think this is considered "Mode 0" as CPOL = 0 and CPHA = 0, since data is clocked in (to the TMP126) on rising edge and out on falling edge.