Other Parts Discussed in Thread: SYSCONFIG
Hi,
We are busy developing a product with the above device using the MMWAVE_L_SDK_05_03_00_02 SDK. One of the things we wish to do is use SPI0 (in peripheral mode) for inter processor communication with a host device (in controller mode). We have got the SPI bus working, but in setting it up have come across a few issues which we hope can be answered here. These are:
1). SPI communication (in MCSPI_OPER_MODE_INTERRUPT mode) doesn't work in the seperate thread when in low power mode, only normal power mode. Is there perhaps something that low power mode does that prevents the peripheral from working. Could it perhaps be related to this setting (.enableSPICSWakeupLPDS) in Power_ConfigV1?
2). In MCSPI DMA mode, we can only get this mode to work with EDMA config 0 (EDMA_APPSS_A) and not config 1 (EDMA_APPSS_B) both in our code and in the demo code in CCS. Can MCSPI be used in DMA mode using EDMA config 1 (EDMA_APPSS_B) and if so, is there perhaps an example we can look at?
3). In MCSPI DMA mode (EDMA config 0), the highest clock rate we can use for stable transfers seems to only be about 10MHz. Can we expect to achieve higher clock rates than this? Our controller device can go up to 32MHz and we see that it is doing this correctly with a logic analyser.
4). In the MCSPI settings, our code only seems to work when these MCSPI_ChConfig settings are as follows:
.inputSelect = MCSPI_IS_D1, .dpe0 = MCSPI_DPE_ENABLE, .dpe1 = MCSPI_DPE_DISABLE,
.inputSelect = MCSPI_IS_D0, .dpe0 = MCSPI_DPE_DISABLE, .dpe1 = MCSPI_DPE_ENABLE,