Other Parts Discussed in Thread: DP83TC812R-Q1
Hi，
The AWR2944EVM supports two RGMII Ethernet ports to provide the connection to the network.One is a MATEnet port (9-2304372-9 connector) via a DP83TC812R-Q1 PHY ,the other is an RJ45 port via a DP83867ERGZR PHY. By default, the RGMII interfaces is connected to the RJ45 port. In the demo, .syscfg file only supports DP83867ERGZR PHY driver. We want to use MATEnet port via a DP83TC812R-Q1 PHY and we have done smoe work.
Firstly in software aspect,I have sucessfully added the DP83TC812R drivers (including DP83TC812.c ,DP83TC812_priv.hand DP83TC812.h files ) to the mcu_plus_sdk_awr294x_08_04_00_22 and ti_board_config.c can be autogenerated as belows:
/*
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/*
* Auto generated file
*/
#include "ti_board_config.h"
/*
* Auto generated file
*/
#include <stdint.h>
#include <enet.h>
#include <networking/enet/core/include/phy/enetphy.h>
#include <networking/enet/core/include/phy/dp83tc812.h>
#include <networking/enet/utils/include/enet_apputils.h>
#include <drivers/hw_include/cslr_soc.h>
#include <networking/enet/core/src/phy/enetphy_priv.h>
#define CONFIG_ENET_CPSW0_PHY0_ADDR (0U)
/* PHY drivers */
extern EnetPhy_Drv gEnetPhyDrvGeneric;
extern EnetPhy_Drv gEnetPhyDrvDp83822;
extern EnetPhy_Drv gEnetPhyDrvDp83867;
extern EnetPhy_Drv gEnetPhyDrvDp83869;
extern EnetPhy_Drv gEnetPhyDrvVsc8514;
extern EnetPhy_Drv gEnetPhyDrvDp83tc812;
/*! \brief All the registered PHY specific drivers. */
static const EnetPhyDrv_Handle gEnetPhyDrvs[] =
{
&gEnetPhyDrvDp83tc812, /* DP83tc812 */
&gEnetPhyDrvGeneric, /* Generic PHY - must be last */
};
const EnetPhy_DrvInfoTbl gEnetPhyDrvTbl =
{
.numHandles = ENET_ARRAYSIZE(gEnetPhyDrvs),
.hPhyDrvList = gEnetPhyDrvs,
};
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
/**
TPR:MSS_CTRL:CPSW_CONTROL
Address offset 0x0000016C
Physical address 0x0212016C
Instance MSS_CTRL
CPSW_CONTROL_RGMII1_ID_MODE 16 Writing 1'b1 would disable the internal clock delays. And those delays need to be handled on board.
CPSW_CONTROL_RMII_REF_CLK_OE_N 8 To select the rmii_ref_clk from PAD or from MSS_RCM. 0: clock will be from mss_rcm through IO internal loopback 1: will be from
CPSW_CONTROL_PORT1_MODE_SEL 2:0 Port 1 Interface
00 = GMII/MII
01 = RMII
10 = RGMII
11 = Not Supported
*/
#define MSS_CPSW_CONTROL_PORT_MODE_RMII (0x1U)
#define MSS_CPSW_CONTROL_PORT_MODE_RGMII (0x2U)
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *ethPort);
static const EnetBoard_PortCfg *EnetBoard_findPortCfg(const EnetBoard_EthPort *ethPort,
const EnetBoard_PortCfg *ethPortCfgs,
uint32_t numEthPorts);
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/*!
* \brief Common Processor Board (CPB) board's DP83867 PHY configuration.
*/
static const Dp83tc812_Cfg gEnetCpbBoard_dp83tc812PhyCfg =
{
.txClkShiftEn = true,
.rxClkShiftEn = true,
.interruptEn = false,
.sgmiiAutoNegEn = true,
.MasterSlaveMode = DP83TC812_MASTER_SLAVE_STRAP,
};
/*
* AM64x board configuration.
*
* 1 x RGMII PHY connected to AM64x CPSW_2G MAC port.
*/
static const EnetBoard_PortCfg gEnetCpbBoard_awr294xEthPort[] =
{
{ /* "CPSW3G" */
.enetType = ENET_CPSW_2G,
.instId = 0U,
.macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
.phyCfg =
{
.phyAddr = 0,
.isStrapped = false,
.skipExtendedCfg = false,
.extendedCfg = &gEnetCpbBoard_dp83tc812PhyCfg,
.extendedCfgSize = sizeof(gEnetCpbBoard_dp83tc812PhyCfg),
},
.flags = 0U,
},
};
/*
* J721E virtual board used for MAC loopback setup.
*/
static const EnetBoard_PortCfg gEnetLpbkBoard_awr294xEthPort[] =
{
{ /* RGMII MAC loopback */
.enetType = ENET_CPSW_2G,
.instId = 0U,
.macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
.phyCfg =
{
.phyAddr = ENETPHY_INVALID_PHYADDR,
},
.flags = 0U,
},
{ /* RMII MAC loopback */
.enetType = ENET_CPSW_2G,
.instId = 0U,
.macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED },
.phyCfg =
{
.phyAddr = ENETPHY_INVALID_PHYADDR,
},
.flags = 0U,
},
};
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
const EnetBoard_PhyCfg *EnetBoard_getPhyCfg(const EnetBoard_EthPort *ethPort)
{
const EnetBoard_PortCfg *portCfg;
portCfg = EnetBoard_getPortCfg(ethPort);
return (portCfg != NULL) ? &portCfg->phyCfg : NULL;
}
static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *ethPort)
{
const EnetBoard_PortCfg *portCfg = NULL;
if (ENET_NOT_ZERO(ethPort->boardId & ENETBOARD_CPB_ID))
{
portCfg = EnetBoard_findPortCfg(ethPort,
gEnetCpbBoard_awr294xEthPort,
ENETPHY_ARRAYSIZE(gEnetCpbBoard_awr294xEthPort));
}
if ((portCfg == NULL) &&
ENET_NOT_ZERO(ethPort->boardId & ENETBOARD_LOOPBACK_ID))
{
portCfg = EnetBoard_findPortCfg(ethPort,
gEnetLpbkBoard_awr294xEthPort,
ENETPHY_ARRAYSIZE(gEnetLpbkBoard_awr294xEthPort));
}
return portCfg;
}
static const EnetBoard_PortCfg *EnetBoard_findPortCfg(const EnetBoard_EthPort *ethPort,
const EnetBoard_PortCfg *ethPortCfgs,
uint32_t numEthPorts)
{
const EnetBoard_PortCfg *ethPortCfg = NULL;
bool found = false;
uint32_t i;
for (i = 0U; i < numEthPorts; i++)
{
ethPortCfg = ðPortCfgs[i];
if ((ethPortCfg->enetType == ethPort->enetType) &&
(ethPortCfg->instId == ethPort->instId) &&
(ethPortCfg->macPort == ethPort->macPort) &&
(ethPortCfg->mii.layerType == ethPort->mii.layerType) &&
(ethPortCfg->mii.sublayerType == ethPort->mii.sublayerType))
{
found = true;
break;
}
}
return found ? ethPortCfg : NULL;
}
int32_t EnetBoard_setupPorts(EnetBoard_EthPort *ethPorts,
uint32_t numEthPorts)
{
CSL_mss_ctrlRegs *mssCtrlRegs = (CSL_mss_ctrlRegs *)CSL_MSS_CTRL_U_BASE;
DebugP_assert(numEthPorts == 1);
DebugP_assert(ethPorts[0].macPort == ENET_MAC_PORT_1);
DebugP_assert(ethPorts[0].mii.sublayerType == ENET_MAC_SUBLAYER_REDUCED);
switch(ethPorts[0].mii.layerType)
{
case ENET_MAC_LAYER_MII:
CSL_FINS( mssCtrlRegs->CPSW_CONTROL,MSS_CTRL_CPSW_CONTROL_CPSW_CONTROL_PORT1_MODE_SEL, MSS_CPSW_CONTROL_PORT_MODE_RMII);
break;
case ENET_MAC_LAYER_GMII:
CSL_FINS( mssCtrlRegs->CPSW_CONTROL,MSS_CTRL_CPSW_CONTROL_CPSW_CONTROL_PORT1_MODE_SEL, MSS_CPSW_CONTROL_PORT_MODE_RGMII);
break;
default:
DebugP_assert(false);
}
/* Nothing else to do */
return ENET_SOK;
}
static const uint8_t gMacAddr[6U] = {
0x70,
0xFF,
0x76,
0x1D,
0xEC,
0xF3
};
void EnetBoard_getMacAddrList(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
uint32_t maxMacEntries,
uint32_t *pAvailMacEntries)
{
EnetAppUtils_assert(pAvailMacEntries != NULL);
memcpy(macAddr, &gMacAddr, ENET_MAC_ADDR_LEN);
*pAvailMacEntries = 1U;
}
/*
* Get ethernet board id
*/
uint32_t EnetBoard_getId(void)
{
return ENETBOARD_AWR294X_EVM;
}
void Board_init(void)
{
}
void Board_deinit(void)
{
}
Is there any error with the configuration for DP83TC812 ?Such as:
static const Dp83tc812_Cfg gEnetCpbBoard_dp83tc812PhyCfg =
{
.txClkShiftEn = true,
.rxClkShiftEn = true,
.interruptEn = false,
.sgmiiAutoNegEn = true,
.MasterSlaveMode = DP83TC812_MASTER_SLAVE_STRAP,
};
static const EnetBoard_PortCfg gEnetCpbBoard_awr294xEthPort[] =
{
{ /* "CPSW3G" */
.enetType = ENET_CPSW_2G,
.instId = 0U,
.macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
.phyCfg =
{
.phyAddr = 0,
.isStrapped = false,
.skipExtendedCfg = false,
.extendedCfg = &gEnetCpbBoard_dp83tc812PhyCfg,
.extendedCfgSize = sizeof(gEnetCpbBoard_dp83tc812PhyCfg),
},
.flags = 0U,
},
};
static const EnetBoard_PortCfg gEnetLpbkBoard_awr294xEthPort[] =
{
{ /* RGMII MAC loopback */
.enetType = ENET_CPSW_2G,
.instId = 0U,
.macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
.phyCfg =
{
.phyAddr = ENETPHY_INVALID_PHYADDR,
},
.flags = 0U,
},
{ /* RMII MAC loopback */
.enetType = ENET_CPSW_2G,
.instId = 0U,
.macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED },
.phyCfg =
{
.phyAddr = ENETPHY_INVALID_PHYADDR,
},
.flags = 0U,
},
};
The configurations are reasonable or not.
If it is, can you point them out?
Secondly in hardware aspect, we have do some changes in the hardware as description in the AWR2944EVM User’s Guide to enable the DP83TC812R PHY.
Besides that, in order to make DP83TC812R work normally, is there any other change that we should do especially in software aspect?
BR,
Rata
