AWR2944PEVM: Connection Error with DDM Demo AWR2944PEVM

Hi Emil,

Can you use a terminal emulator like Tera Term and check if you see the below logs when connected to Application/User UART? Ensure that the COM port is not utilized by any other application. For example, if you are connected to Tera Term, you cannot establish connection in the visualizer.

Regards,

Samhitha

Hey,

When using tera term to connect to the AWR2944PEVM flashed with the mmw_ddm enet demo, we see the output like in your screenshot. However, when flashing the radar with the awr2x44P_ccsdebug.appimage appimage and load the mmw_ddm enet demo using CCS 20.2.0, tera term only displays an empty terminal and does accept any input. This prevents us from configurating and starting the sensor. The debug output in CCS from the R5 Cortex is the following:
Cortex_R5_0: **********************************************
Cortex_R5_0: Debug: Launching the MMW Demo on MSS
Cortex_R5_0: **********************************************
Cortex_R5_0: Debug: Launched the Initialization Task
Cortex_R5_0: BSS is powered up...
Cortex_R5_0: Debug: mmWave Control Initialization was successful
Cortex_R5_0: Debug: mmWave Control Synchronization was successful
Cortex_R5_0: EnetPhy_bindDriver:1863 
Cortex_R5_0: PHY 0 is alive
Cortex_R5_0: Starting lwIP, local interface IP is dhcp-enabled
Cortex_R5_0: [LWIPIF_LWIP] NETIF INIT SUCCESS
Cortex_R5_0: Host MAC address-0 : 70:ff:76:1d:ec:f2
Cortex_R5_0: Enet IF UP Event. Local interface IP:0.0.0.0
Cortex_R5_0: [LWIPIF_LWIP] Enet has been started successfully
Cortex_R5_0: Enet IF UP Event. Local interface IP:192.168.1.200
Cortex_R5_0: Waiting for network UP ...
Cortex_R5_0: Waiting for network UP ...
Cortex_R5_0: Cpsw_handleLinkUp:1626 
Cortex_R5_0: MAC Port 1: link up
Cortex_R5_0: Network Link UP Event
Cortex_R5_0: Network is UP …

Hi Emil,

I suggest you to run mmw_ddm demo without ENET first. Ensure that you perform CPU reset followed by loading program on each of the core. Click on "Run" to run application on each core one after the other i.e do not group the cores and run.

Regards,

Samhitha

Hey Samhitha,

Thanks for the quick response. We've already tried without ENET when doing the initial debugging. 

Emil,

Emil K said:

We've already tried without ENET when doing the initial debugging. 

Did you face any issues while testing with DDM demo without ENET? 

Are facing issues only while using DDM ENET demo? Can you confirm if you have run all the cores one after the other?

Regards,

Samhitha

Hi Samhitha,

Thanks for following up. Here is what we are seeing:

- DDM without ENET: Same problem. The CLI on User UART never shows a prompt or accepts input, so the visualizer cannot configure or start the sensor.  
- DDM ENET vs. TDM: Problem appears in DDM (UART-only) and DDM ENET. TDM demo works with the same procedure.  
- Core run order: We do CPU Reset, then load and run C66x first, then R5F, one after the other. We also tried the reverse order, result is the same.

Two reproducible paths

1) Flashed prebuilt mmw_ddm_enet appimage (SDK 04.07.01.04):
   * Tera Term on User UART prints logs similar to your example.
   * R5F console shows that the interface receives an address and link comes up.
   * After closing Tera Term and switching to the DDM visualizer, connection still fails (CLI open -> timeout).

2) awr2x44P_ccsdebug.appimage + load DDM (ENET and non-ENET) from CCS (TI tools 20.2.0):
   * R5F debug shows the init and network sequence.
   * User UART stays blank and does not respond, so no CLI commands can be issued.

Other details
* Connected on Application/User UART, with no port conflicts when starting the visualizer.
* Performed power-cycle and CPU Reset between attempts.
* UART configuration is correct, since TDM demo connects and responds with the same setup.

Is there a known difference in how the CLI/UART is initialized in DDM on AWR2944 with mmwave_mcuplus_sdk_04_07_01_04 (especially with ENET enabled)? The stack and link appear fine, but the CLI does not become responsive in DDM, blocking both UART commands and visualizer connection.

Happy to test a patch or alternative configuration if you suggest one.

Emil K

I can see that three binary files are created when compiling the DDM demo: awr2x44P_mmw_demo_dss_cm4DDMEnet.xem4, awr2x44P_mmw_demo_dssDDMEnet.xe66, awr2x44P_mmw_demo_mssDDMENET.xer5f. In CCS, there are only two cores which I am able to connect to, the Cortex_R5_0 and C66xx_DSP.

Currently, we load the .xe66 binary to the C66xx_DSP core followed by the loading of the .xer5f binary to the Cortex_r5_0 core. Which core should the .xem4 binary be loaded to? I have tried to load the binaries in the following order .xe66->C66xx_DSP, .xer5f->Cortex_R5_0, .xem4->C66xx_DSP, but when doing this I get the following error:

C66xx_DSP: Trouble Reading Memory Block at 0x0 on Page 0 of Length 0x4: (Error -1176 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.2.0.3536) 
C66xx_DSP: File Loader: Verification failed: Target failed to read 0x00000000
File: C:\ti\mmwave_mcuplus_sdk_04_07_01_04\mmwave_mcuplus_sdk_04_07_01_04\ti\demo\awr2x44P\mmw_ddm\awr2x44P_mmw_demo_dss_cm4DDMEnet.xem4: Load failed.C66xx_DSP: GEL: File: C:\ti\mmwave_mcuplus_sdk_04_07_01_04\mmwave_mcuplus_sdk_04_07_01_04\ti\demo\awr2x44P\mmw_ddm\awr2x44P_mmw_demo_dss_cm4DDMEnet.xem4: Load failed.

Does the order in which the binaries are loaded matter? Also, could you provide how/order you loaded the binaries to the cores and which cores you loaded each binary to.

Thanks