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AWR2944: Is the RCM region read-only? Which modules can access the RCM? How are the permissions of the RCM region configured?

cheyrl wang
Intellectual 910 points
Part Number: AWR2944


Is the RCM region read-only? Which modules can access the RCM? How are the permissions of the RCM region configured?How to configure RCM permissions through the MPU? What are the default permissions of the RCM region?  

  • 0
    TI__Prodigy 490 points

    Hi,

    In general the RCM (Reset & Clock Management) regions are read and write both, unless user configures them to be "read-only" through MPU.
    Can you also please specify what do you mean by "modules" ? 
    If you are referring to different cores, yes all cores can access the RCM region in a non-secured device.

    For information on how to configure permissions in MPU, you may refer to API guide present at this location in your SDK
    Location : "mmwave_mcuplus_sdk_04_07_01_04\mcu_plus_sdk_awr294x_10_01_00_04\docs\api_guide_awr294x"
    In this HTML guide navigate to "AWR294x MCU + SDK > API Reference > APIs for Driver Porting Layer > APIs for MPU".

    By default the RCM regions are read & write both.

    Thanks,
    Harsh 

  • 0 in reply to Harsh Bardhan
    Intellectual 910 points

    Hi,Harsh

        For Functions 

          SOC_rcmStartMemInitTCMA();
          SOC_rcmWaitMemInitTCMA();
          SOC_rcmStartMemInitTCMB();
          SOC_rcmWaitMemInitTCMB(); ,Where are these functions positioned in the overall initialization process? Do they need to be placed after certain modules, such as the basic clock and reset control?
  • 0 in reply to cheyrl wang
    TI__Prodigy 490 points

    Hi,

    Here is a general initialization sequence.

    RBL > SBL 

    Within SBL the following sequence takes place on a high level.

    Configuring APLLs > Load cores (R4, C66) > Run core (R4, C66) > R4 boot check > Load core (R5)  > Run core (R5). 

    After Loading cores (R4, C66), we initialize the TCMA, TCMB memories calling these functions: 

     SOC_rcmStartMemInitTCMA();
     SOC_rcmWaitMemInitTCMA();
     SOC_rcmStartMemInitTCMB();
     SOC_rcmWaitMemInitTCMB();

    You may also refer to the following main file for more information.

    path : "mmwave_mcuplus_sdk_04_07_01_04\mcu_plus_sdk_awr294x_10_01_00_04\examples\drivers\boot\sbl_qspi\awr294x-evm\r5fss0-0_nortos\main.c"

    Inside the int main (void) function, you can find the initialization sequence.


    Yes, these functions are to be placed after PLLs are configured and CpuPowerOnResest is done for R4, C66.


    Thanks,
    Harsh
  • 0 in reply to Harsh Bardhan
    Intellectual 910 points

    In the custom SBL code, the interrupt information is stored in TCM. If I load the application code from external FLASH into RAM before jumping to the APP, how should I handle the TCM initialization function?

  • 0 in reply to cheyrl wang
    TI__Prodigy 490 points

    Hi,

    The TCM initialization functions are generally called after the cores are initialized i.e. the applications are loaded on to the cores. 


    During the RBL phase, the interrupt information stored in the TCM is different from the one we want in the SBL phase, in SBL we load the application's IVT from the flash.

    Thanks,
    Harsh
      

  • 0 in reply to Harsh Bardhan
    Intellectual 910 points

    In the custom SBL code, the interrupt vector table is placed in TCMA.

    Question 1: Why does the SBL crash when I put the functions
    SOC_rcmStartMemInitTCMA();
    SOC_rcmWaitMemInitTCMA();
    inside the SBL initialization function?

    Question 2: Assuming I put the functions
    SOC_rcmStartMemInitTCMA();
    SOC_rcmWaitMemInitTCMA();
    before loading the application program, why does the SBL still work normally after the application loading fails? Why doesn’t it crash like in Question 1?

  • 0 in reply to Harsh Bardhan
    Intellectual 910 points

    When TCMA initialization is placed before the APP loading, will the SBL’s critical code and interrupt vector table migrate to other secure memory?

  • 0 in reply to cheyrl wang
    TI__Prodigy 490 points

    Hi,

    Can you please share what all functions you are placing inside SBL initialization? If that's possible.

    Typically, SBL's IVT is needed during the SBL phase. 


    Thank you,
    Harsh

  • 0 in reply to Harsh Bardhan
    Intellectual 910 points
    uint32 SBL_Init(uint16 cfg, const NvMBL_Def_t* pAppNvmDef)
    {
       /*Make sure public interface definition matches*/
       /*Otherwise we need to implment a mapping*/
       ASSERT_STATIC(FBLS_E_INIT_DEFAULT == CLK_IF_INIT_DEFAULT);
       ASSERT_STATIC(FBLS_E_INIT_ETH == CLK_IF_INIT_ETH);

       uint32 status = FBLS_E_OK;
       /* Extract init configuration bits */
       uint16 initCfg = FBLS_EXTRACT_INIT_BIT(cfg);

       /* initialize Hwi but keep interrupts disabled */
       HwiP_init();

       CycleCounterP_init(SOC_rcmGetR5Clock());
       /* Initialize Clocks */
       if (ClkIf_Init(initCfg) == FALSE)
       {
          status |= FBLS_E_CLKIF_INIT;
       }

       /* Init Memory: Initialize the C66x subsystem as the DSS_L3 memory is used to store libs or ppar data */
       SOC_rcmStartMemInitDSSL3(SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL);
       SOC_rcmWaitMemInitDSSL3(SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL);
       /* Initialize Timer HW */
       Bl_SstInit();

       if(BLCOM_StructureCheck() != BLCOM_OK)
       {
          /* The BLCom data is invalid, clear share ram data */
          if(BLCOM_ClearSharedRam() != BLCOM_OK)
          {
             status |= FBLS_E_RETRAM_INIT;
          }
          /* Valid BLCom data */
          BLCOM_FblInit();
       }
       DMA_Init();

       /*Copy reset register*/
       FBLS_SetRsrCopy();

       /* Initialize Flash Interface */
       if(FLU_Init() != E_OK)
       {
          status |= FBLS_E_FLU_INIT;
       }

       /*Initialize PPAR*/
       status |= Bl_PparInit();
       
       /*Init pin driver common pins*/
       Bl_PinsInitCommon();

       /*Init pin driver trcv pins*/
       if(Bl_PinsInitTrcv() == FALSE)
       {
          status |= FBLS_E_TRCVPIN_INIT;
       }
       /*Init can addr and can transiver */
       FBLS_AddrInit();
       FBLS_TrxCtrlInit();
       /*Initialize MSS_BOOT_INFO_REG2 & REG3, for HP and SP Init state*/
       HW_WR_REG32_RAW(MSS_BOOT_INFO_REG_ADDR(INFO_HP_STATE_IDX), 0x00);
       HW_WR_REG32_RAW(MSS_BOOT_INFO_REG_ADDR(INFO_SP_STATE_IDX), 0x00);
       
       SOC_rcmStartMemInitTCMA();
       SOC_rcmWaitMemInitTCMA();

       FBLS_SetLibVersion(FBL_SLOT_FBLS, FBL_SUPPORT_LIBRARY_TYPE, FBL_SUPPORT_VERSION, FBL_SUPPORT_SUBVERSION);
       return status;
    }