TMP1826: DC level violation with 3.3V Processor (OSD6254).

Part Number: TMP1826
Other Parts Discussed in Thread: SN74LVC1G07

Hi Team,

Posting on behalf of our customer.

I am performing a DC analysis for a new design using the TMP1826NGRR as a 1-Wire temperature sensor, and I have identified a logic level violation regarding the threshold when operating at 3.3V.

System Parameters:

  • VCC/VPUR/Vs: 3.3V
  • Host Processor: OSD6254-1G-IPM
  • Sensor: TI TMP1826NGRR
  • Interface: 1-Wire (SDQ)

The Violation:

According to the TMP1826 datasheet, the Input Logic High Level (VIH) is defined as 0.8 x Vs. At a supply of 3.3V, this results in a VIH (min) of 2.64V.

However, my host processor (OSD6254) specifies a VOH(min) of only 2.4V. This creates a negative noise margin of -0.24V, where the processor's minimum "High" output does not meet the sensor's minimum input voltage requirement.

Can you please confirm whether this apparent VIH violation affects data read/write operation between the host SoC and TMP1826, and whether it can be resolved solely by an appropriate external pull-up resistor on the open-drain SDQ line or if a level shifter is required.

Please suggest the appropriate resolution.

Regards,

Danilo