LM95234 About SMBus characteristics

Hi Kato-san,

I will look into this, get back to you soon.

Aaron

Hi Kato-san,

Based on the SMBus specs, the maximum bus speed is 100kHz. This translate to a minimum SMBCLK low time of (1/100kHz) * 0.5 = 5000ns, which is already a long time after our data has finished switching.

However, if they use a higher speed master (for example, I2C at fast mode which operates at 400kHz) for some reason, then this number will be critical. The SCL low time is only 1250ns. If our data settled at 1050ns, it may be not provide enough setup time for the master to sample our SDA properly (200ns only).

I hope this helps. Please let me know if you have further question. Thanks.

Aaron

Hi Aaron - san

I have a question about the reply.

In case of clock frequency 50kHz  as follows,

Can I set Data hold time is near 5us?

I don't understand why tHD;DAT's max limits is defined and why 1075ns.

Best Regards,

Kato

Hi Kato-san,

Slowing the clock shouldn't be a problem. I don't quite sure what you mean by setting hold time. As long as you don't capture the LM95234 SDA from 300ns to 1050ns after SCL falling edge, you should be ok.

Aaron

HI Aaron - san ,

I understood that tHD-DAT is the delay time of  SMBDAT output.

Is it correct?

In that case, why  is min-300ns provided?

Best Regards,

Kato