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TMP401 - Open Drain Digital Output Pins (_THERM, _ALERT/_THERM2)

Other Parts Discussed in Thread: TMP401

Hello,

My customer has a question about TMP401.

[Background]

The descriptions of _THERM pin and _ALERT/_THERM2 pin are described in the datasheet as follows.

_THERM : Thermal flag, active low, open-drain; requires pull-up resistor to V+

_ALERT/_THERM2 : Alert (reconfigurable as second thermal flag), active low, open-drain; requires pull-up resistor to V+

[Q]

Is it impossible that these pins are pulled up to other voltage in spite of the open drain ?

Best Regards,

Hiroshi Katsunaga

  • Hi Hiroshi-san,

    I will get back to you.

    Aaron
  • Hi Aaron-san,

    Thank you for your fast response.
    OK, I will wait your reply.

    Best Regards,
    Hiroshi Katsunaga
  • Hi Hiroshi-san,

    I'm sorry for the long delay. We normally not recommended connecting these pins directly to other voltage. These pins are open drain, which mean it can only drive a signal low, it requires the pull up resistor to bring its high.

    Aaron
  • Hi Aaron-san,

    Thank you for your response.

    I recognize that the feature of general open drain circuits are as follows.

    (1) It can only drive a signal low, therefore it requires the pull up resistor to bring its high. (This is your comment.)

    (2) The users can select the pull up voltage of the pull up resistor because the specifications of the receiver have many use case.

          For example 1.8VLVCMOS, 2.5VLVCMOS, 3.3VLVCMOS, and so on...

    (3) The maximum pull up voltage of the pull up resistor is limited by Absolute Maximum Ratings of the open drain pins.

    (4) The users can use some open drain circuits with the common pull up resistor as wired AND.

    I understand that it require the pull up resistor.

    However, I don't understand that it require the pull up resistor to V+.

    [Q]

    Again, why is it to V+ ? Should it not be other voltage ?

    Best Regards,

    Hiroshi Katsunaga

  • Hi Hiroshi-san,

    You can connect these pins to other voltage as long as you can maintain the logic level without violating the abs max. In my opinion, the safest path is connecting to V+ preventing from latch up the ESD structure when the other voltage power sequence occur before V+.

    Assuming there are two voltages call vdd2 and vdd1.

    When the vdd2 > vdd1, a true open-drain output (as specified in the datasheet for SCL/SDA and typically ALERT pins as well as THERM) doesn't have a path from the pin to supply. There is only a gate from the pin to ground. As long as there is no path to supply; it shouldn't be an issue with this pin exceeding device's V+.

    However, it could be a problem when design these pins incorrectly. It can place a gate to supply.
    When this happens, the pin is not truly open-drain, and it cannot exceed device's V+, and violating the absolute max.

    When vdd2 < vdd1, it would be violating the logic level specs and excessive current float into the pin; however, it shouldn't damage the device. But I wouldn't recommended doing this, and it's better prevent this from happening.

    Hope this helps!

    Aaron
  • Hi Aaron-san,

    Thank you for your fast response.
    I understood your comments.

    I will recommend the pull-up voltage for open-drain V+.

    Thank you for your cooperation.

    Best Regards,
    Hiroshi Katsunaga