TMP102-Q1: SCL low to SAD output valid (tvd)

cafain

Part Number: TMP102-Q1
Other Parts Discussed in Thread: TMP102

Hi,

Please let me question at Two-Wire timing of TMP102-Q1.
Data sheet for TMP102-Q1 (SBOS702C) page12 Two-Wire Timing Diagram is shown in Figure8.

I am at data timing, the time from when SCL goes low until SDA becomes valid I want to know.
However, it is not shown in Figure8.

Although it is a device, the I2C Interface Timing Requirements of PCA9524
"Tvd (data) Valid data time (SCL low to SDA output valid)" is regulated.

Please tvs of TMP102-Q1.

best regards

over 7 years ago

0 Ren Schackmann over 7 years ago

TI__Mastermind 35825 points

Hi cafain,

I was unable to find information regarding PCA9524.

TMP102 does not have a requirement for Tvd. As long as the other requirements are met, there is no issue with Tvd.

Thanks,
Ren

0 cafain over 7 years ago in reply to Ren Schackmann

Mastermind 6365 points

Hi, Ren-san

I appreciate the reply.

In the I2C standard, the specification of tVD: DAT has been added from Revision 3.0,

Is the I2C specification of TMP102-Q1 Revision3(I2C Rev) or earlier?
(For example, I2C of TMP102-Q1 was designed with I2C-Rev 2.0)

best regards

cafain

0 Ren Schackmann over 7 years ago in reply to cafain

TI__Mastermind 35825 points

Hi cafain-san,

TMP102 was released in 2007, so it was designed prior to the release of I2C v3 in 2007.

Ren

0 cafain over 7 years ago in reply to Ren Schackmann

Mastermind 6365 points

HI, Ren-san

Thank you for explaining, I appreciate it.

If problems occur, please support again.

best regard

Sensors

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TMP102-Q1: SCL low to SAD output valid (tvd)