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TMP709: Power-up behavior from 0V to 2.7V

Part Number: TMP709

I'm using this part into a 2 transistor regenerative latch in a high noise RF environment (1/4" away from a 150W RF power transistor).  I have generally eliminated noise issues, but I need to know what the power-up behavior of the TMP709 is because the latch following it may be active from 0.5V up to 5V.  The TMP709 power supply is a zener regulated 5.1V, but depends on a customer-provided (28V) external power supply whose ramp-up profile is not known.  I need to verify the TMP709's characteristic behavior (not specified, of course) between 0V and 2.7v to see under what conditions the latch may be triggered during a power-up event.  The latch will trigger on about 10 ua of current sunk by the /OT pin, within 50 us.  The supply will come up no faster than 2 ms (RC time constant of 2.43k/1uf bypass cap.)

The SET pin and /OT pin are each bypassed with 1 nF NP0 for RF suppression.  Power supply bypass is 1 uf // 5.1V zener.  Pullup R 44.2k to 5V.

ESD immunity at 28V side of power supply on PCB assy next to latch with en61000-4-2 ESD contact discharge parameters, except 200 ps rise time, latch trigger threshold (Criteria C) is +/- 10kv, contact discharge, about 1/2" away from the latch.

  • Adding bypass capacitance to the SET pin will directly delay biasing of the external set resistor. This could cause the kind of power-on behavior that you're seeking to avoid. Note that the device typically consumes 40uA, and this includes the current which it sources on the SET pin in order to bias the set resistor. I would recommend not using a capacitor here, or using a very small value with characterization.

  • I see your concern about the biasing dellay.  I have a challenging compromise to achieve here.  This circuit is in a very high noise RF environment where up to 10A of RF current at 40 MHz is flowing, with on-off keying at up to 500 kHz and highly variable RF loading (so the noise immunity has to be excellent.) The SET R is at 37.4k at the moment, and may be adjusted  down a few percent in the future.

    We can easily tolerate up to 1 second of startup delay as long as false triggering does not occur during the 0V-2.7V transition phase.  The current RC (discharge) time constant on the SET pin is about 37 us with a 1000 pf C, with R dominating after about 5 time constants, roughly 185 us.

    Also, after looking at the datasheet, won't the capacitor delay on the SET pin drive the temperature threshold higher while the capacitor on the SET pin is charging?  Or is the comparator going to be ouside its CM range and falsely turn on the NMOS?  Or will some other transition behavior I don't know about occur?

    Based on your response, I need some information to base my capacitor testing on the SET pin on, to balance RF suppression and avoiding false trips:

    1.  What is the comparator, reference and internal NMOS speed on the TMP709, so I can establish a reasonable RC time constant that is much faster than the speeds of the comparator and NMOS output driver?

    2.  What is the bias current on the SET pin so I can ensure the correct voltage value is established long before the comparator can respond?

    Best Regards,

    -Gordon Wood

    RF EE

    Access Laser Co.

  • Hi Gordon,

    1. I can't share this information about the design.
    2. You can assume the bias current is no more than 40uA.

  • Thanks for the info you were able to give.

    I'll test for what's needed, then.

    Best Regards,

    -Gordon Wood

    RF EE

    Access Laser  Co.