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DRV411: H_bridge output voltage swing

Part Number: DRV411

Dear TI engineer,

In the datasheet, I saw that the output voltage of the H bridge can reach 5V which is the VDD of DRV411 when the compensation current is small (R_load is very high). I can't understand it because I think that the output voltage should be near 1 volt lower than VDD due to the influence of the Vgs of up & low MOSFET in H bridge.

Could you help to explain how it realized or the datasheet is wrong?

  • Hello Ocean,

    Thanks for using the forum to get your question answered.  I only found the specification below which is a swing across the Bridge at 4.2V with a supply of 5V and 20 ohms load. I could not find in the datasheet the statement you mentioned.  Can you please attach it for my reference.

    If you are worried about the output protection mentioned in the datasheet this is due to the compensation coil acting transformer and causing voltage spikes on the h-bridge that could exceed the supply rails and must be protected against.

  • Hi Javier,

    I forgot to attach the picture. Below is the screen short. This figure is on page 8. So the question is how the output voltage of H bridge can reach VDD? Where is the Vgs of the MOSFET or Vbe of the bip transistor on H Bridge? Or the figure is wrong?

  • Ocean,

    The reason it can get to the higher voltage swings is because the limiting factor is the On-Resistance.  The high side are controlled by PFET and the low side by NFET.  The Gate voltages are controlled by internal logic and are able to go to the supply rails to turn of the FETs or lower voltages to turn them on.  The VGS will be plenty to turn on the FETs. 

    Hope this clarifies.

  • Hi Javier,

    I got it. I used to think that H bridge has a NMOS upper and PMOS lower. Because this can keep the common mode voltage of the COMP1 and COMP2 to near VCC/2. Now it seems that this IC use a PMOS upper and NMOS lower. This can explain the question I ask.

    But in another hand, I guess that the PMOS and NMOS must be matched very well to keep the common mode voltage of COMP1 AND COMP2 to near VCC/2. Is my guess correct?

  • Ocean,

    I am positive there is additional circuitry that bias the output voltage common mode voltage to VCC/2.