Other Parts Discussed in Thread: TIDEP-01012
Hi,
We have a cascaded design of AWR1243 chipset (master + x1 slave). We would like to understand the impact of boot up/initial calibration performed in such configuration of the chip. We are now making a call to rlRfInitCalibConfig with calibEnMask set to 0xFFF. Then, we make the call to rlRfInit as per documentation. We have parsed the AWR_AE_RF_INITCALIBSTATUS_SB response from both master and slave chips:
We have the following questions:
- In yellow: APLL tuning/calibration seems to be performed and succeeds only for slave chip. Does it make sense? We have a shared LO loop-backed to the master in our design.
- In green: our chirp configuration starts at 76 GHz, thus employing VCO1 according to the documentation. However, response says that even both synthesizer VCOs calibration are triggered, only VCO1 calibration is successful for master chip while not for slave and the opposite happens with VCO2. Why?
- In red: we employ one TX channel from master chip. Therefore, master TX phase calibration must be performed. However, slave fails to calibrate it. Is it consistent?
- In blue: CALIBRATION_UPDATE field shows that 3 fields will not be updated for the slave but will for the master. Could it be that calibration results are within specs and therefore no tuning is needed?
To our understanding, profile/chirping configuration happens after calibration so any calibration must be performed independently of actual profile parameters. Could you please confirm that?
Thanks for your feedback in advance,
M.
